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Stuart McCracken

dblp:24/956 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2002
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Reconfigurable computing and FPGAs · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › VLSI testing
FPGA interconnect testing		 0.012002
FPGA test time reduction through a novel interconnect testing scheme · FPGA 2002
Electronic design automation
hardware verification and test		 0.012002
FPGA test time reduction through a novel interconnect testing scheme · FPGA 2002
Electronic design automation › hardware verification and test
test application time reduction		 0.012002
FPGA test time reduction through a novel interconnect testing scheme · FPGA 2002
Reconfigurable computing and FPGAs
FPGA testing		 0.012002
FPGA test time reduction through a novel interconnect testing scheme · FPGA 2002

Methods — techniques the papers use, named apart from their topics

feedback shift register · 0.0
YearPublicationVenuePosition
2002 FPGA test time reduction through a novel interconnect testing scheme
abstract
As device densities increase, testing cost is becoming a larger portion of the overall FPGA manufacturing cost. We present an approach to speed up testing FPGA interconnect by reconfiguring it during the test. Simple additions are made to create feedback shift register structures, which considerably reduce the number of test configurations for the switching matrix interconnect. This new testing architecture reduces switching matrix test time by 66% and the diagnosis time by 72%. The additions are transparent to the users both in terms of speed and functionality.
Stuart McCracken, Zeljko Zilic
 FPGA1