Demo Data from EDBT 2026 / reviewers in the wild / expert
Jiazhen Lin
dblp:240/9420
· DBLP profile ↗
8ranked-venue papers
1as first author
5since 2021 · last 2026
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 since 2021Artificial intelligence and machine learning · 2 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
5 papers |
Distributed systems · 25% Electronic design automation · 17% Processor architecture and microarchitecture · 17% | |
| Artificial intelligence
2 papers |
Efficient and distributed learning · 100% | |
| Databases, data mining, and information retrieval
2 papers |
Recommender systems · 58% Machine learning and data management · 42% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 17 heaviest of 18, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Operating systems › resource management › process management
CPU scheduling |
0.8 | 1 | 2024 | Fast Core Scheduling with Userspace Process Abstraction · SOSP 2024 |
Processor architecture and microarchitecture › chip multiprocessor
core scheduling |
0.8 | 1 | 2024 | Fast Core Scheduling with Userspace Process Abstraction · SOSP 2024 |
Electronic design automation › high-level synthesis
scheduling |
0.8 | 1 | 2024 | Fast Core Scheduling with Userspace Process Abstraction · SOSP 2024 |
GPUs and heterogeneous computing
GPU computing |
0.6 | 1 | 2022 | Fleche: an efficient GPU embedding cache for personalized recommendations · EuroSys 2022 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.6 | 1 | 2022 | Fleche: an efficient GPU embedding cache for personalized recommendations · EuroSys 2022 |
Cloud and datacenter computing
request scheduling |
0.6 | 1 | 2022 | AlNiCo: SmartNIC-accelerated Contention-aware Request Scheduling for Transaction Processing · USENIX ATC 2022 |
Distributed systems
transaction processing |
0.6 | 1 | 2022 | AlNiCo: SmartNIC-accelerated Contention-aware Request Scheduling for Transaction Processing · USENIX ATC 2022 |
Machine learning and data management
continual learning |
0.4 | 1 | 2020 | Kraken: memory-efficient continual learning for large-scale real-time recommendations · SC 2020 |
Recommender systems
large-scale recommendation |
0.4 | 1 | 2020 | Kraken: memory-efficient continual learning for large-scale real-time recommendations · SC 2020 |
Distributed systems › distributed machine learning
parameter server |
0.4 | 1 | 2020 | Kraken: memory-efficient continual learning for large-scale real-time recommendations · SC 2020 |
Machine learning › Efficient and distributed learning
low-precision training |
0.4 | 1 | 2019 | Differentiable Soft Quantization: Bridging Full-Precision and Low-Bit Neural Networks · ICCV 2019 |
Machine learning › Efficient and distributed learning
model compression |
0.4 | 1 | 2019 | Differentiable Soft Quantization: Bridging Full-Precision and Low-Bit Neural Networks · ICCV 2019 |
Machine learning › Efficient and distributed learning › model compression › quantization
quantized neural network |
0.4 | 1 | 2019 | Differentiable Soft Quantization: Bridging Full-Precision and Low-Bit Neural Networks · ICCV 2019 |
Recommender systems
neural recommendation |
0.2 | 1 | 2022 | Fleche: an efficient GPU embedding cache for personalized recommendations · EuroSys 2022 |
Hardware accelerators and domain-specific architectures › network accelerator
SmartNIC |
0.2 | 1 | 2022 | AlNiCo: SmartNIC-accelerated Contention-aware Request Scheduling for Transaction Processing · USENIX ATC 2022 |
Machine learning › Efficient and distributed learning
memory-efficient training |
0.1 | 1 | 2020 | Kraken: memory-efficient continual learning for large-scale real-time recommendations · SC 2020 |
Distributed systems › edge computing
edge deployment |
0.1 | 1 | 2019 | Differentiable Soft Quantization: Bridging Full-Precision and Low-Bit Neural Networks · ICCV 2019 |
Methods — techniques the papers use, named apart from their topics
userspace interrupts · 1.5memory protection keys · 1.5sparsity-aware training · 1.3learning optimizers · 1.3kernel merging · 1.1embedding table caching · 1.1gradient approximation · 0.8differentiable soft quantization · 0.8contention-aware scheduling · 0.6SmartNIC acceleration · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Evidential learning driven breast tumor segmentation with stage-divided vision-language interaction
Jingxing Zhong, Qingtao Pan, Xuchang Zhou, Jiazhen Lin, Xinguo Zhuang |
Neurocomputing | 4 |
| 2024 | Fast Core Scheduling with Userspace Process AbstractionabstractWe introduce uProcess, a pure userspace process abstraction that enables CPU cores to be rescheduled among applications at sub-microsecond timescale without trapping into the kernel. We achieve this by constructing a special privileged mode in userspace to achieve safe and efficient separation among uProcesses. The core idea is a careful combination of two emerging hardware features - userspace interrupts (Uintr) and memory protection keys (MPK). We materialize the uProcess abstraction by implementing Vessel, a userspace core scheduler that colocates latency-critical and best-effort applications with minimal switching overhead when they time-share CPU cores. Our experiment result shows that Vessel exhibits better overall performance and low latency when multiple applications are colocated. Jiazhen Lin, Youmin Chen, Youyou Lu |
SOSP | 1 |
| 2022 | Fleche: an efficient GPU embedding cache for personalized recommendationsabstractDeep learning based models have dominated current production recommendation systems. However, the gap between CPU-side DRAM data accessing and GPU processing still impedes their inference performance. GPU-resident cache can bridge this gap, but we find that existing systems leave the benefits to cache the embedding table, a huge sparse structure, on GPU unexploited. In this paper, we present Fleche, a holistic cache scheme with detailed designs for efficient GPU-resident embedding caching. Fleche (1) uses one cache backend for all embedding tables to improve the total cache utilization, and (2) merges small kernel calls into one unitary call to reduce the overhead of kernel maintenance (e.g., kernel launching and synchronizing). Furthermore, we carefully design the cache query workflow for finer-grain parallelism. Evaluations with real-world datasets show that compared with the prior art, Fleche significantly improves the throughput of embedding layer by 2.0 -- 5.4×, and gets up to 2.4× speedup of end-to-end inference throughput. Minhui Xie, Youyou Lu, Jiazhen Lin, Qing Wang 0031, Jiwu Shu |
EuroSys | 3 |
| 2022 | AlNiCo: SmartNIC-accelerated Contention-aware Request Scheduling for Transaction Processing
Youyou Lu, Qing Wang 0031, Jiazhen Lin, Zhe Yang 0012, Jiwu Shu |
USENIX ATC | 4 |
| 2021 | An IVC-Based Nuclear Emergency Parallel Evacuation SystemabstractNuclear emergency evacuation is challenging and dangerous, with time constraints, resource limitations, and radiation exposure risks. The development of the Internet of Things (IoT) and artificial intelligence enables us to build an intelligent evacuation system to help mitigate this problem a great deal. In this article, we design the nuclear emergency parallel evacuation system based on the artificial systems (A), computational experiments (C), and parallel execution (P) approach and intelligent vehicle collaborative systems (IVCs). In this system, the evacuation risks of different regions under various possible scenarios are simulated and evaluated in the artificial systems. With data adversarially generated from the artificial systems and collected from sensors all over the area, an optimization model is proposed to find the optimal evacuation plans for emergent evacuation scenarios in the computational experiments. Eventually, the most suitable running strategy of autonomous buses will be selected and carried out based on the parallel execution in accordance with the real scene. A case study is conducted, and results indicate that the system can serve as an efficient tool for future nuclear emergency evacuation planning. Linyao Yang, Xin Liu 0022, Yancai Xu, Jiazhen Lin, Xiao Wang 0002, Fei-Yue Wang 0001 |
IEEE Trans. Comput. Soc. Syst. | 5 |
| 2020 | Kraken: memory-efficient continual learning for large-scale real-time recommendationsabstractModern recommendation systems in industry often use deep learning (DL) models that achieve better model accuracy with more data and model parameters. However, current opensource DL frameworks, such as TensorFlow and PyTorch, show relatively low scalability on training recommendation models with terabytes of parameters. To efficiently learn large-scale recommendation models from data streams that generate hundreds of terabytes training data daily, we introduce a continual learning system called Kraken. Kraken contains a special parameter server implementation that dynamically adapts to the rapidly changing set of sparse features for the continual training and serving of recommendation models. Kraken provides a sparsity-aware training system that uses different learning optimizers for dense and sparse parameters to reduce memory overhead. Extensive experiments using real-world datasets confirm the effectiveness and scalability of Kraken. Kraken can benefit the accuracy of recommendation tasks with the same memory resources, or trisect the memory usage while keeping model performance. Minhui Xie, Youyou Lu, Guangxu Yang, Qingxing Xu, Bihai Wu, Jiazhen Lin, Hongbo Ao, Wanhong Xu, Jiwu Shu |
SC | 7 |
| 2019 | A Web-based Remote FPGA Laboratory for Computer Organization CourseabstractLearning in digital systems could be enhanced by applying a learn-by-doing mechanism. In this paper the implementation of a web-based remote FPGA laboratory for Computer Organization course is proposed. The projects created for this course are designed towards entry-level users thus producing a trouble-free virtualization of experimental equipment that in turn maximizes educational gain. The network laboratory had made learners complete all the experimental activities through the Internet without the limitation of time, space and resources. We show also some preliminary results compared between Fall 2016 and Fall 2017 semester, which highlight improved student engagement, learning and achievement. Han Wan, Kangxu Liu, Jiazhen Lin, Xiaopeng Gao |
ACM Great Lakes Symposium on VLSI | 3 |
| 2019 | Differentiable Soft Quantization: Bridging Full-Precision and Low-Bit Neural NetworksabstractHardware-friendly network quantization (e.g., binary/uniform quantization) can efficiently accelerate the inference and meanwhile reduce memory consumption of the deep neural networks, which is crucial for model deployment on resource-limited devices like mobile phones. However, due to the discreteness of low-bit quantization, existing quantization methods often face the unstable training process and severe performance degradation. To address this problem, in this paper we propose Differentiable Soft Quantization (DSQ) to bridge the gap between the full-precision and low-bit networks. DSQ can automatically evolve during training to gradually approximate the standard quantization. Owing to its differentiable property, DSQ can help pursue the accurate gradients in backward propagation, and reduce the quantization loss in forward process with an appropriate clipping range. Extensive experiments over several popular network structures show that training low-bit neural networks with DSQ can consistently outperform state-of-the-art quantization methods. Besides, our first efficient implementation for deploying 2 to 4-bit DSQ on devices with ARM architecture achieves up to 1.7× speed up, compared with the open-source 8-bit high-performance inference framework NCNN [31]. Ruihao Gong, Xianglong Liu 0001, Shenghu Jiang, Jiazhen Lin, Fengwei Yu |
ICCV | 6 |