Demo Data from EDBT 2026 / reviewers in the wild / expert
Igor Lukyanchuk
dblp:241/0380
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2020
0000-0001-8622-3552ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 38% Electronic design automation · 38% Memory systems · 23% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design
multivalued logic circuit |
0.4 | 1 | 2020 | Development of Programmable Logic Array for Multiple-Valued Logic Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Electronic design automation › logic synthesis
programmable logic array |
0.4 | 1 | 2020 | Development of Programmable Logic Array for Multiple-Valued Logic Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Memory systems
emerging memory technologies |
0.1 | 1 | 2020 | Development of Programmable Logic Array for Multiple-Valued Logic Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Memory systems › non-volatile memory
ferroelectric memory |
0.1 | 1 | 2020 | Development of Programmable Logic Array for Multiple-Valued Logic Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Methods — techniques the papers use, named apart from their topics
logic design · 0.4generalized reed-muller expression · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Development of Programmable Logic Array for Multiple-Valued Logic FunctionsabstractThe binary information technology reaches its limits set by the atomic size miniaturization, by calculation speed and by the fundamental principle of energy dissipation per bit processing. Employing multiple-valued logic (MVL) cells as computing and memory units reduces energy losses and enables to pack of unprecedented high-density information, but the current silicon-based material technologies have been studied marginally for the material realization of MVL devices. Here, we propose to use the ferroelectrics for the implementation of MVL units using their ability to pin the polarization as a sequence of multistable states. More specifically, the realization of a programmable logic array (PLA) based on MVL units is considered with the application of the ferroelectrics technology in implementation of memory units. The specific of the PLA construction is the use of generalized Reed-Muller expression for the representation of an MVL function. In this article, several possible implementations of such PLAs are considered, and their properties are analyzed from the logic design point of view. Vitaly G. Levashenko, Igor Lukyanchuk, Elena N. Zaitseva, Miroslav Kvassay, Jan Rabcan, Patrik Rusnak |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |