The high-energy particles in space cause SRAM failures. The vulnerability of SRAM increases at lower technology, and it flips the SRAM cell’s data due to single-event multi-node-upset. Various state-of-the-art radiation hardened by design SRAMs have been proposed; however, most designs tackle Single Node Upset (SNU). This paper presents DNU Tolerant Quadruple-16T (DTQ-16T) SRAM with no read disturb. The most important feature of the proposed design is its immunity towards radiation, where it recovers from all possible upsets, whether SNU, DNU, Triple Node Upset (TNU), or Quadruple Node Upset (QNU) for storage ‘1’. On top of it, the proposed design gives very high read stability, Write Access Time, and Wordline Write Trip Voltage (WWTV) than most of the existing radiation-hardened SRAMs. Finally, the post-layout and Monte Carlo simulations validate the efficiency of the proposed SRAM in commercial CMOS 28nm technology.

The vulnerability of radiation-induced Single Node Upset (SNU) and Double Node Upset (DNU) on SRAM increase at lower technology nodes. Various state-of-the-art solutions, such as Quatro-10T, DICE cell, etc., have been proposed. Quatro-10T recovers from SNU using the negative feedback networks connected to storage nodes. However, Quatro-10T is not entirely immune to SNU. DICE cell is resistant to SNU, but the design suffers from DNU. In this paper, we propose a Radiation Hardened Sextuple Cross Coupled-16T (RHSCC-16T) SRAM, which is immune to SNU for all the cases and DNU for many cases with less area requirement as compared to DICE cell. In addition, it gives better read access time, write access time, read static noise margin, and wordline write trip voltage than many compared SRAMs. The proposed design possesses 1.54 ×, 1.54 ×, 1.54×, and 1.36× shorter read access time than STD-6T, Quatro-10T, RHM-12T, and RSP-14T. It also exhibits 11.25 ×, and 1.03 × higher read static noise margin than RHM-12T ×and STD-6T and 2.01× higher wordline write trip voltage than Quatro-10T @ VDD = 0.9 V at CMOS 28nm Technology.

This paper presents a split wordline 6T SRAM based compute-in-memory subarray with variable multi-bit precision for input operands and outputs. The split wordlines of the 6T cell enable sign segregation, thus allowing arbitrary sign/magnitude multiply and accumulate (MAC) operations. The arbitrary signmagnitude MAC operation extends the usage of the MAC array for DSP workloads as well. On top of that, the split wordline 6T cell is more resilient to write-disturb, which is a major concern for conventional 6T cell based compute-in-memory operation. The proposed system was designed and implemented using 65nm UMC technology and the energy efficiency and throughput are found to be 80.1 TOPS/W and 496 GOPS respectively, for maximum precision of inputs(4 bits)/outputs(5 bits). The maximum throughput and energy efficiency of the design are found to be 780 GOPS and 94.8 TOPS/W respectively. Hand-written digit recognition application mapped on the proposed system showed a maximum accuracy degradation of 0.2% as compared to that obtained from software with the same input/output quantization.