We present a solution for reducing the number of defective analog/RF integrated circuits (ICs) that escape detection during manufacturing testing. Also known as underkill, these ICs may fail when deployed in their target application and eventually become customer returns, casting doubt on the effectiveness of the employed test solution and affecting the bottom line. To ameliorate this problem, we introduce an adaptive outlier detection solution that identifies ICs which are suspect of becoming customer returns and proactively bins them as failing. The outlier detection boundary used by our method is dynamically computed based on the performance distribution of devices on each wafer and the underlying model is updated when new ICs are returned from customers and failure analysis confirms that they are indeed defective devices. The effectiveness of our method in reducing underkill while minimizing the incurred yield loss is evaluated using an industrial dataset from Texas Instruments.

As quality expectations of integrated circuits (ICs) continue to rise, contemporary semiconductor manufacturing and test solutions experience increased pressure to prevent any defective parts from being shipped, even if this comes at the cost of sacrificing yield. Known as “overkill”, this lost yield is essentially the result of overly conservative decisions made to compensate for imperfect silicon, imperfect test, as well as uncertainties related to the application wherein a fabricated IC will be eventually deployed. Such decisions are often driven by auxiliary production characterization or quality control tests and processes, which are not directly related to the specifications of a product but, rather, mainly reflect the test environment. Nevertheless, based on these tests and in an effort to err on the side of caution, industry often scraps a small yet not insignificant percentage of perfectly good devices. To address this problem and judiciously recover a portion of the yield that is left on the table without increasing risk, we introduce a machine-learning based solution which exploits the correlation between specification tests and auxiliary tests in order to independently assess confidence in the validity and significance of the latter, for which limits are empirically defined. Effectiveness of our method is evaluated using an industrial dataset provided by Texas Instruments.

Post-fabrication performance calibration, a.k.a. trimming, is an essential part of analog/RF IC manufacturing and testing. Its objective is to counteract the impact of process variations by individually fine-tuning the performance parameters of every fabricated chip so that they meet the design specifications and, thereby, to ensure both high yield and high performance. The prevalent trimming process currently employed in industry involves a search algorithm which consists of repeated digital trim-code selection and measurement in order to optimize the trimmed performance. With hundreds of trims commonly performed on contemporary analog/RF chips, this process becomes overly expensive. In this work, we discuss a machine learning-based approach that ameliorates this problem by leveraging inter-trim correlation. Specifically, our method relies on effectively trained regression models which use the measurements obtained through an intelligently selected and conventionally performed subset of trims, in order to accurately predict the optimal trim codes for the omitted trims. Thereby, as corroborated using data from an actual analog/RF IC currently in production, trim time can be drastically reduced without significantly affecting the accuracy of the selected trim codes.

To combat the effects of process variation in modern, high-performance integrated Circuits (ICs), various post-manufacturing calibrations are typically performed. These calibrations aim to bring each device within its specification limits and ensure that it abides by current technology standards. Moreover, with the increasing popularity of mobile devices that usually depend on finite energy sources, power consumption has been introduced as an additional constraint. As a result, post-silicon calibration is often performed to identify the optimal operating voltage (Vmin) of a given Integrated Circuit. This calibration is time-consuming, as it requires the device to be tested in a wide range of voltage inputs across a large number of tests. In this work, we propose a machine learning-based methodology for reducing the cost of performing the Vmincalibration search, by identifying the optimal wafer-level search parameters. The effectiveness of the proposed methodology is demonstrated on an industrial dataset.

Automated defect inspection in manufacturing of microscopic probes is an important task and often requires machine learning driven solutions. A supervised only approach can be challenging, because production manufacturing process typically have few defects, thus large amounts of labeled training data are generally not available. In this work, we instead employed multiple models in a multi-step process to achieve the end goal of identifying defect and non-defect probe tips.

We propose a machine learning-based solution for noise classification and decomposition in RF transceivers. Wireless transmitters are affected by various noise sources, each of which has a distinct impact on the signal constellation points. The proposed approach takes advantage of the characteristic dispersion of points in the constellation by extracting key statistical and geometric features that are used to train a machine learning model. The trained model is, then, capable of identifying the noise source fingerprint, comprised by single or multiple noise sources, for each affected device. Effectiveness of the model has been verified using constellation measurements from a combined set of simulated and actual silicon devices.