Continuous-flow microfluidic biochips (CFMBs) are advanced platforms that precisely manipulate fluids through micron-scale channels and have been widely applied in biomedical research and disease diagnostics. Their internal architecture typically employs multiplexer-based control logic, where control channels transmit input signals to flow valves to dynamically switch fluid paths and achieve precise control. However, the reuse and elimination operations of control channels introduce a large number of L-shaped structures. These structures are prone to channel deformation and, under high-frequency usage, can accelerate structural fatigue, thereby reducing the reliability of the control logic. In addition, improper control channel reuse may lead to signal conflicts and interference. To address these problems, we propose a control logic architecture design approach for CFMBs that simultaneously considers channel length and straightness. First, we propose a placement preprocessing strategy that integrates a heuristic initialization with a critical-path-first approach to improve the quality of the initial placement and ensure feasibility. Second, we design a placement algorithm based on discrete particle swarm optimization with a twin-swarm cooperative mechanism, which effectively explores better placement solutions through cooperative search between the two swarms and feedback from routing results. Finally, we propose a two-stage routing algorithm that integrates error recovery and reuse constraints. By incorporating straightened routing and reasonable reuse, this algorithm significantly reduces channel length and the number of bends while ensuring the correctness of the control logic. Experimental results demonstrate that the proposed approach enables reliable control of flow valves with fewer resources and effectively reduces signal propagation delay in control channels, significantly enhancing the overall performance and reliability of the control logic.

Erasure coding is an effective technique for guaranteeing data reliability for storage systems, yet it incurs a high repair penalty with amplified repair traffic. The repair becomes more intricate in clustered storage systems with the bandwidth diversity property. We present TPRepair , a T ree-based P ipelined Repair approach, aiming to expedite the overall repair process with the tailored pipelined repair procedure. TPRepair first prioritizes selecting racks with the current minimum load to participate in the repair process. It subsequently formulates tree-based links, tailored to align seamlessly with the pipelined repair procedure. TPRepair further designs an optimization algorithm to reduce the bottleneck load when repairing multiple chunks. Large-scale simulations demonstrate that TPRepair can increase 13.8%–41.3% of the balance ratio without amplifying cross-rack traffic. Meanwhile, Alibaba Cloud ECS experiments indicate that TPRepair can increase repair throughput by 11.3% to 72.9%.

Continuous-flow microfluidic biochips are gaining increasing attention with promising applications for automatically executing various laboratory procedures in biology and biochemistry. Biochips with distributed channel-storage architectures enable each channel to switch between the roles of transportation and storage. Consequently, fluid transportation, caching, and fetch can occur concurrently through different flow paths. When two dissimilar types of fluidic flows occur through the same channels in a time-interleaved manner, it may cause contamination to the latter as some residues of the former flow may be stuck at the channel wall during transportation. To remove the residues, wash operations are introduced as an essential step to avoid incorrect assay outcomes. However, existing work has been considered that the washing capacity of a buffer fluid is unlimited. In the actual scenario, a fixed-volume buffer fluid irrefutably possesses a limited washing capacity, which can be successively consumed while washing away residues from the channels. Hence, capacity-aware wash scheme is a basic requirement to fulfil the dynamic fluid scheduling and channel storage. In this paper, we formulate a practical wash optimization problem for microfluidic biochips, which considers the requirements of dynamic fluid scheduling, channel storage, as well as washing capacity constraints of buffer fluids simultaneously, and present an efficient design flow to solve this problem systematically. Given the high-level synthesis result of a biochemical application and the corresponding component placement solution, our goal is to complete a contamination-aware flow-path planning with short flow-channel length. Meanwhile, the biochemical application can be executed efficiently and correctly with an optimized capacity-aware wash scheme. Experimental results show that compared to a state-of-the-art washing method, the proposed method achieves an average reduction of 26.1%, 43.1%, and 34.1% across all the benchmarks with respect to the total channel length, total wash time, and execution time of bioassays, respectively.

Continuous-flow microfluidic biochips have emerged as a potential low-cost and fast-responsive lab-on-chip platform. They have attracted much attention due to their capability of performing various biochemical applications concurrently and automatically within a coin-sized chip area. To improve execution efficiency and reduce fabrication cost, a distributed channel-storage architecture can be implemented in which the same channels can be switched between the roles of transportation and storage. Accordingly, fluid transportation, caching, and fetch can be performed simultaneously through different flow paths. Such a flow-path planning needs to be considered carefully in the mapping procedure from a biochemical application to a given biochip architecture. Moreover, all the on-chip valves should be actuated correctly and promptly to temporally block the fluid transportation in unwanted directions and seal the fluids in caching channels. Such an exact control of the valves needs to be considered systematically in control-system design to support the mapping scheme for bioassay execution. In this article, we formulate the practical mapping-control co-design problem for microfluidic biochips with distributed channel storage, considering application mapping, valve synchronization, and control-system design simultaneously, and present an efficient synthesis flow to solve this problem systematically. Given the protocol of a biochemical application and the corresponding chip layout in the flow layer, our goal is to map the biochemical application onto the chip with short execution time. Meanwhile, a practical control system considering the real valve-switching requirements can be constructed efficiently with low fabrication cost. Experimental results on multiple real-life bioassays and synthetic benchmarks demonstrate the effectiveness of the proposed design flow.

System-architecture design optimization of flow-based microfluidic biochips has been extensively investigated over the past decade. Most of the prior work, however, is still based on chip architectures with dedicated storage units and this, not only limits the performance of biochips, but also increases their fabrication cost. To overcome this limitation, a distributed channel-storage architecture can be implemented, where fluid samples can be cached temporarily in flow channels instead of using a dedicated storage. This new concept of fluid storage, however, requires a careful arrangement of fluid samples to enable the channels to fulfill the dual functions of transportation and caching. Moreover, to avoid cross-contamination between different fluidic flows, wash operations are necessary to remove the residue left in flow channels. In this article, we formulate the first practical system level design and wash optimization problem for microfluidic biochips with distributed channel storage architecture, considering high-level synthesis, physical design, and wash optimization simultaneously, and present a top-down design flow to solve this problem systematically. Given the protocol of a biochemical application and the corresponding design requirements, our goal is to generate a chip architecture with low fabrication cost. Meanwhile the biochemical application can be executed efficiently with an optimized wash scheme. Experimental results on multiple benchmarks confirm that our approach leads to short completion time of biochemical applications, low chip cost, as well as high wash efficiency.

Flow-based microfluidic biochips (FBMBs) have attracted much attention over the past decade. On such a micrometer-scale platform, various biochemical applications, also called bioas-says, can be processed concurrently and automatically. To improve execution efficiency and reduce fabrication cost, a distributed channel-storage architecture (DCSA) can be implemented on this platform, where fluid samples can be cached temporarily in flow channels close to components. Although DCSA can improve the execution efficiency of FBMBs significantly, it requires a careful arrangement of fluid samples to enable the channels to fulfill the dual functions of transportation and caching. In this paper, we formulate the first flow-layer physical design problem considering DCSA, and propose a top-down synthesis algorithm to generate efficient solutions considering execution efficiency, washing, and resource usage simultaneously. Experimental results demonstrate that the proposed algorithm leads to a shorter execution time, less flow-channel length, and a higher efficiency of on-chip resource utilization for biochemical applications compared with a direct approach to incorporate distributed storage into existing frameworks.