With the advancement of 3D IC technology, multilayer chip stacking enables improved performance and reduced power consumption, albeit at the cost of increased design complexity. In 3D IC designs, soft modules are also adopted to enable flexible floorplanning across multiple dies. To preserve module integrity and simplify interconnects, the standard cells and macros within the same module are typically constrained to be placed on the same layer and thus using the same technology. In addition, determining an appropriate shape and placement location for each soft module is critical for minimizing wirelength. This paper presents the first technology-aware 3D placement framework for mixed-size designs that incorporates region planning for soft modules. It combines an analytical placement engine with an integer linear programming (ILP)-based region planning strategy to handle the flexible nature of soft modules. To further enhance placement flexibility while limiting region complexity, the ILP formulation identifies an optimal L-shaped or rectangular region for each soft module. Experimental results demonstrate that, compared to a baseline approach, our flow achieves over 21% wirelength reduction, with only a 5% overhead compared to placement without the soft module constraint.

Contemporary semiconductor fabrication nodes present escalating challenges in achieving optimal power-performance-area (PPA) trade-offs, necessitating sophisticated optimization methodologies for digital circuit design. The 2025 ICCAD CAD Contest Problem B [1] introduces significant advances in multibit flip-flop optimization research, establishing a comprehensive benchmarking framework that bridges theoretical algorithm development with practical industrial implementation requirements. This enhanced contest platform, building upon the foundational work of the 2024 iteration [2], delivers unprecedented contributions to the electronic design automation (EDA) research community through mandatory operation traceability protocols, industry-standard LEF/DEF format integration, and enhanced computational resource allocation (16-core processing capability). Our primary research contribution establishes a rigorous validation infrastructure that enables comprehensive algorithmic transparency while addressing real-world optimization challenges encountered in production semiconductor design flows. The framework introduces innovative research enablers including complete transformation audit trails, cross-platform validation compatibility, and systematic performance evaluation under authentic design constraints. Through strategic banking and debanking optimization techniques, research participants engage with fundamental circuit optimization trade-offs while contributing to the advancement of multibit flip-flop optimization science. The enhanced 2025 framework provides the global research community with unprecedented insights into algorithm behavior patterns, transformation correctness verification methodologies, and scalable performance characteristics—essential foundations for advancing state-of-the-art multibit flip-flop optimization research.

In modern designs, timing performance, power, and area constraints (PPA) are the three major metrics for physical design. 2024 ICCAD CAD Contest Problem B investigates the optimization of power, area, and timing in modern semiconductor designs through the strategic use of multibit flip-flops. By banking flip-flops, more area can be freed up, and also efficiently reduce power consumption and reduce net routing complexity. While multibit flip-flop banking has been effective in reducing power and area, it could negatively impact timing performance in critical paths, thus multibit flip-flop debanking could be performed to alleviate timing critical paths. 2024 ICCAD CAD Contest Problem B presents a challenge where participants must optimize the virtual designs by dynamically applying banking and debanking techniques to achieve optimized trade-offs among PPA.

In the chiplet era, the benefits from multiple factors can be observed by splitting a large single die into multiple small dies. By having the multiple small dies with die-to-die (D2D) vertical connections, the benefits including: 1) better yield, 2) better timing/performance, and 3) better cost. How to do the netlist partitioning, cell placement in each of the small dies, and also how to determine the location of the D2D inter-connection terminals becomes a new topic.

With the development of semiconductor technology nodes, the sizes of standard cells become smaller and the number of standard cells is dramatically increased to bring into more functionality in integrated circuits (ICs). However, the shrinking of standard cell sizes causes many problems of ICs such as timing, power, and electromigration (EM). To tackle these problems, a new style structural pre-route (SPR) is proposed. Such type of pre-route is composed of redundant parallel metals and vias so that the low resistance and the redundant sub-structures can improve timing and yield. But the large area overhead becomes the major problem of inserting such pre-routes all over a design. In this paper, we propose a machine learning-based approach to predict the insertability of SPRs for placed designs. In addition, we apply a pattern visualization method by using a guided backpropagation technique to see in depth of our model and identify the problematic layout features causing SPR insertion failures. The experimental results not only show the excellent performance of our model, but also show that avoiding generating the identified critical features during legalization can improve SPR insertability compared to a commercial SPR-aware placement tool.

2021 ICCAD CAD Contest Problem B is an extended problem from 2020 ICCAD CAD Contest Problem B [1]–[2] for addressing more complex constraints. In the physical implementation, the common approach is to divide the problem into the placement and routing stage. By doing this divide-and-conquer approach, it may cause conservative margin reservation and miscorrelation. In order to achieve multiple advanced objectives in terms of Power, timing Performance and Area, so called PPA, a certain amount of cell movement at the routing stage become a desired functionality in an EDA tool. 2021 ICCAD CAD Contest Problem B encourages the research in the techniques of routing with cell movement to achieve multiple objectives in the advanced process nodes (less than 7 nm). We provided (i) a set of benchmarks and (ii) an evaluation metric of multiple objectives including power factor, the criticality of timing critical nets, the maximum number of moving cells, and the total routing length optimization that facilitate contestants to develop and test their new algorithms.

With the continuous scaling down of process nodes, standard cells become much smaller and cell counts are dramatically increased. Pin accessibility becomes one of the major issues causing design rule violations (DRVs). To tackle this problem, many recent works apply machine-learning-based techniques to predict whether a local region has DRV or not by regarding global routing (GR) congestion and local pin density as the main features during the training process. Empirically, however, DRV occurrence is not necessary to be strongly correlated with the two features in advanced nodes. In this article, we propose the first work of deep-learning-based DRV prediction using pin pattern as our major feature to directly identify whether a DRV will exist or not due to bad pin accessibility of the given pin pattern. Unlike most of the existing models that can only be used for DRV prediction, the proposed models can be applied to guide detailed placement for pin accessibility optimization during physical design. Experimental results show that the proposed models are greatly superior than those of previous studies in terms of all quantitative metrics. Additionally, the numbers of DRVs can be dramatically reduced by applying the proposed model-guided detailed placement flow.

In advanced semiconductor processes, the dramatic shrink of layout features has made a significant impact on circuit delay and electromigration (EM). Recently, meshed stack vias (MSVs) have been proposed as a solution to improve circuit timing and signal integrity, each of which is a multi-layer mesh structure composed of parallel metal shapes and vias. Due to the introduced MSV rules and more and more complicated design rules, MSV design becomes a very challenging problem, while no previous work has addressed this issue. In this paper, we propose the first work of MSV design by developing two different methods: an integer linear programming (ILP)-based and a dynamic programming (DP)-based methods. Unlike most previous works devoting themselves to formulating sophisticated constraints for each complicated design rule, we propose an automatic constraint generation (ACG) framework to iteratively resolve design rule violations (DRVs) without any effort in understanding all design rules, which contributes to a general MSV design methodology applicable to different technology nodes. Experimental results show that both the ILP-based and DP-based approaches can averagely achieve 92% MSV insertion rate for a set of industrial benchmarks. In addition, by adopting the proposed ACG framework, 100% MSV insertion rate can be achieved without causing any DRV.

With the development of advanced process nodes of semiconductor, the problem of pin access has become one of the major factors to impact the occurrences of design rule violations (DRVs) due to complex design rules and limited routing resource. Many state-of-the-art works address the problem of DRV prediction by adopting supervised machine learning approaches. However, those supervised learning approaches extract the labels of training data by generating a great number of routed designs in advance, giving rise to large effort on training data preparation. In addition, the pre-trained model could hardly predict unseen data and thus may not be applied to predict other designs containing cells that are not used in the training data. In this paper, we propose the first work of cell library-based pin accessibility prediction (PAP) by using active learning techniques. A given set of standard cell libraries is served as the only input for model training. Unlike most of existing studies that aim at design-specific training, we propose a library-based model which can be applied to all designs referencing to the same standard cell library set. Experimental results show that the proposed model can be applied to predict two different designs with different reference library sets. The number of remaining DRVs and M2 shorts of the designs optimized by the proposed model are also much fewer than those of design-specific models.

With the continuous scaling down of process nodes, standard cells become much smaller and cell counts are dramatically increased. Pin accessibility becomes one of the major issues causing design rule violations (DRVs). To tackle this problem, many recent works apply machine learning-based techniques to predict whether a local region has DRV or not by regarding global routing (GR) congestion and local pin density as the main features during the training process. Empirically, however, DRV occurrence is not necessary to be strongly correlated with the two features in advanced nodes. In this paper, we propose the first work of deep learning-based DRV prediction using pin pattern as our major feature to directly identify whether a DRV will exist or not due to bad pin accessibility of the given pin pattern. Unlike most of existing models that can only be used for DRV prediction, the proposed models can be applied to guide detailed placement for pin accessibility optimization during physical design. Experimental results show that the proposed models are greatly superior than those of previous studies in terms of all quantitative metrics. Additionally, the numbers of DRVs can be dramatically reduced by applying the proposed model-guided detailed placement flow.

In physical implementation, the quality of net open location finder would directly impact the quality of final routing result. It is important to consider both of the length of indicated paths and the turnaround time. To address this problem, the ICCAD-2017 contest encourages the research in obstacle-aware multi-layer shortest paths finding and the corresponding speedup techniques. We provided (i) a set of benchmarks and (ii) an evaluation metric that facilitate contestants to develop and test their new algorithms.