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Demo Data from EDBT 2026 / reviewers in the wild / expert

Md Asif Shahjalal

dblp:241/4355 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › layout verification
design rule checking		 0.412019
Predicting DRC Violations Using Ensemble Random Forest Algorithm · DAC 2019
Electronic design automation › physical design › layout verification
design rule violation prediction		 0.412019
Predicting DRC Violations Using Ensemble Random Forest Algorithm · DAC 2019
Electronic design automation
physical design		 0.412019
Predicting DRC Violations Using Ensemble Random Forest Algorithm · DAC 2019
Electronic design automation › physical design
routing		 0.412019
Predicting DRC Violations Using Ensemble Random Forest Algorithm · DAC 2019

Methods — techniques the papers use, named apart from their topics

support vector machine · 0.4random forest · 0.4ensemble learning · 0.4
YearPublicationVenuePosition
2019 Predicting DRC Violations Using Ensemble Random Forest Algorithm
abstract
At leading technology nodes, the industry is facing a stiff challenge to make profitable ICs. One of the primary issues is the design rule checking (DRC) violation. In this research, we cohort with the DARPA IDEA program that aims for "no-human-in-the-loop" and 24-hour turnaround time to implement an IC from design specifications. In order to reduce human effort, we introduce the ensemble random forest algorithm to predict DRC violations before global routing, which is considered the most time-consuming step in an IC design flow. In addition, we identified features that critically impact the DRC violations. The algorithm has a 5.8% better F1-score compared to the existing SVM classifiers.
Riadul Islam, Md Asif Shahjalal
 DAC2