As conventional CMOS technology approaches power and performance limits, superconducting single flux quantum (SFQ) logic offers a path to high-speed, energy-efficient computing. However, SFQ circuits require cryogenic temperatures, introducing complex challenges in memory integration and data movement between thermal zones. This paper presents an end-to-end simulation framework for hybrid SFQ/CMOS-memory systems that accurately models processor, memory, and interconnect behavior across cryogenic $(4 \mathrm{~K}, 77 \mathrm{~K})$ and room temperatures $(300 \mathrm{~K})$. The framework integrates gate-level pipelined Rapid SFQ (RSFQ) RISC-V processors, temperature-aware CryoMEM memory models, and physically grounded interconnect latency models. The simulator facilitates cross-layer design space exploration across diverse parameters such as cache placement, interconnect stack selection, and granularity. These features allow the community to identify technological gaps and re-evaluate the bottlenecks in memory-compute throughput. Our evaluations highlight the critical interplay between processor frequency and memory bandwidth, demonstrate the speedup potential of 4K SFQ caches, and quantify the impact of cryostat cabling choices on system performance.

Superconductor-semiconductor interface circuits are integral part of connecting cryogenic classical and quantum computing systems with the room temperature electronics. Due to the cooling power constraints of cryogenic setups, the number of data transmission channels between temperature stages is often limited by the heat load of cables and connectors. As a result, a high data rate (throughput) per channel is desired for large-scale computing systems. The state-of-the-art superconductor-semiconductor interface circuits use a binary data format. In this work, a novel interface circuit is proposed that produces signals with pulse-amplitude modulation (PAM). As a case study, a PAM-4 SQUID (superconducting quantum interference device) stack interface circuit is developed. With four output voltage levels, the effective data rate can be doubled while keeping the same operating frequency. Alternatively, the number of cryogenic cables can be reduced by two times as compared to the conventional binary data links.

With the growing interest in emerging and upcoming quantum computers, it is important to consider possible hardware security vulnerabilities and countermeasures. This work proposes side-channel attacks targeting classical-quantum interface circuits in superconducting quantum computers. Particularly, a single flux quantum (SFQ) technology-based classical controller, which is a promising candidate for large-scale in-fridge qubit control and readout circuitry, is considered. We have uncovered a substantial side-channel leakage from superconducting interface circuits through the power supply variations. An attacker, who has access to room temperature electronics where the power is generated, can successfully decode certain information about various components within quantum computers.

Cryogenic testing and verification of single-flux quantum (SFQ) circuits consist of various challenges, such as limited number of input–output pins, flux trapping, and cooling power constraints. Developing design for testability (DFT) techniques for SFQ circuits, which address these challenges, is an important research area. In this work, a built-in self-test (BIST) methodology of SFQ circuits is proposed, which focuses on a novel way of the readout of test signals by using side-channel leakage information. The side-channel leakage can exhibit the dependence of internal data (logical “1” and “0”) on the power consumption. By measuring the variations in the power supply of an SFQ circuit at room temperature, the information about internal test signal states can be extracted with the proposed BIST methodology. As a case study, a rapid SFQ (RSFQ) 4-to-2 priority encoder circuit is considered. The existing Josephson junction (JJ)-based stuck-at fault model is applied with the proposed BIST methodology. The proposed BIST design is compared with a conventional shift register-based readout circuitry. The proposed BIST design can provide 79% lower static power consumption and 65% lower layout area. In addition, other advantages and drawbacks of the proposed design are discussed, such as yield, number of pins, testing time, interpretation of test results, and hardware security.

The proposed converter is designed for low power applications. In this paper, the algorithm is proposed to solve the coupled case of dual input and the dual output converter. The major contribution is R-parameters calculation for the coupled case is deliberated in detail where it includes all conduction and ohmic losses accounting for coupling effects. To validate the performance of designed SCC, modeling and mathematical analysis has been carried out. The results are verified using PSIM simulations and validated mathematically. The analytical and simulation results give excellent proof for the newly designed coupled converter.