Jyotika Athavale

dblp:241/8296 · DBLP profile ↗
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5ranked-venue papers
1as first author
4since 2021 · last 2024
0000-0001-6427-2687ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-author · 4 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 1 since 2021
YearPublicationVenuePosition
2024 Innovation Practices Track: Advances on Silicon Lifecycle Reliability, Safety and Security
abstract
Silicon Lifecycle Management (SLM) has emerged as a strategic solution to address the challenges on meeting increasing silicon production quality and in-field dependability requirements. In this Innovation Practices track, we invited industry experts to discuss the advances in silicon lifecycle reliability, safety and security domains, respectively.
Jyotika Athavale, Marc Witteman
VTS2
2023 Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections
abstract
Assessing the reliability of modern devices running CNN algorithms is a very difficult task. Actually, the complexity of the state-of-the-art devices makes exhaustive Fault Injection (FI) campaigns impractical and typically out of the computational capabilities. A possible solution consists of resorting to statistical FI campaigns that allow a reduction in the number of needed experiments by injecting only a carefully selected small part of it. Under specific hypothesis, statistical FIs guarantee an accurate picture of the problem, albeit selecting a reduced sample size. The main problems today are related to the choice of the sample size, the location of the faults, and the correct understanding of the statistical assumptions. The intent of this paper is twofold: first, we describe how to correctly specify statistical FIs for Convolutional Neural Networks; second, we propose a data analysis on the CNN parameters that drastically reduces the number of FIs needed to achieve statistically significant results without compromising the validity of the proposed method. The methodology is experimentally validated on two CNNs, ResNet-20 and MobileNetV2, and the results show that a statistical FI campaign on about 1.21% and 0.55% of the possible faults, provides very precise information of the CNN reliability. The statistical results have been confirmed by the exhaustive FI campaigns on the same cases of study.
Annachiara Ruospo, Gabriele Gavarini, Corrado De Sio, Juan-David Guerrero-Balaguera, Luca Sterpone, Matteo Sonza Reorda, Ernesto Sánchez 0001, Riccardo Mariani, Joseph Aribido, Jyotika Athavale
DATE10
2023 Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs
abstract
The widespread use of artificial intelligence (AI)-based systems has raised several concerns about their deployment in safety-critical systems. Industry standards, such as ISO26262 for automotive, require detecting hardware faults during the mission of the device. Similarly, new standards are being released concerning the functional safety of AI systems (e.g., ISO/IEC CD TR 5469). Hardware solutions have been proposed for the infield testing of the hardware executing AI applications; however, when used in applications such as Convolutional Neural Networks (CNNs) in image processing tasks, their usage may increase the hardware cost and affect the application performances. In this paper, for the very first time, a methodology to develop high-quality test images, to be interleaved with the normal inference process of the CNN application is proposed. An Image Test Library (ITL) is developed targeting the on-line test of GPU functional units. The proposed approach does not require changing the actual CNN (thus incurring in costly memory loading operations) since it is able to exploit the actual CNN structure. Experimental results show that a 6-image ITL is able to achieve about 95% of stuck-at test coverage on the floating-point multipliers in a GPU. The obtained ITL requires a very low test application time, as well as a very low memory space for storing the test images and the golden test responses.
Annachiara Ruospo, Gabriele Gavarini, Antonio Porsia, Matteo Sonza Reorda, Ernesto Sánchez 0001, Riccardo Mariani, Joseph Aribido, Jyotika Athavale
ETS8
2022 Test, Reliability and Functional Safety Trends for Automotive System-on-Chip
abstract
This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life.
Francesco Angione, Davide Appello, Joseph Aribido, Jyotika Athavale, Nicolò Bellarmino, Paolo Bernardi 0002, Riccardo Cantoro, Corrado De Sio, Tommaso Foscale, Gabriele Gavarini, Juan-David Guerrero-Balaguera, Martin Huch, Giusy Iaria, Tobias Kilian, Riccardo Mariani, Raffaele Martone, Annachiara Ruospo, Ernesto Sánchez 0001, Ulf Schlichtmann, Giovanni Squillero, Matteo Sonza Reorda, Luca Sterpone, Vincenzo Tancorre, Roberto Ugioli
ETS4
2019 Flight Safety Certification Implications for Complex Multi-Core Processor based Avionics Systems
abstract
Since the early 1990s, federated avionics architecture - where one computing resource executes only one application, is being replaced by Integrated Modular Avionics (IMA) architectures. IMA architectures employ a partitioned environment that hosts multiple avionics functions of different safety criticalities on a common computing platform. This provides for size, weight, and power savings via denser functional integration. Several cores integrated onto one device allows more functions to be integrated together on one processor and in one piece of equipment. The use of multicore processors in safety-critical avionics applications will provide growth for further integration for the future generations of these systems. Hence aerospace equipment suppliers are interested in using Multi-Core Processors (MCPs) in their systems. With the rapid increase in demand for computational performance and cost optimum, Single-Core Processors (SCPs) are likely to become obsolete. However, with the shift to multi-core processors, compliance to safety requirements is becoming critical. The development and use of increasingly complex electronic hardware by the aviation industry for more of the safety-critical aircraft functions is creating new safety and certification concerns.
Jyotika Athavale, Riccardo Mariani, Michael Paulitsch
IOLTS1