Due to the numerous advantages of dual-band infrared radiation (DBIR) attitude measurement (AM) technology, it has garnered significant attention from industry and academia. However, geometric errors caused by sensor measurement noise, assembly positions, motor interference and other sensor-related commonalities, along with random errors induced by the sensitivity of DBIR characteristics to infrared radiation interference, collectively undermine the reliability of the estimated attitude information. To address this issue, the bidirectional gated recurrent unit (Bi-GRU) and Transformer were combined to assist extended kalman filter (EKF) for DBIR attitude estimation (CBGTE). The core concept involves two aspects: 1) utilizing EKF to mitigate geometric errors during the process of DBIR AM, and 2) combining Bi-GRU and Transformer to aid EKF in compensating for random errors in the measurement process. A semi-physical experimental platform is established to validate the performance of CBGTE. Through experimental validation with real-world data, the proposed CBGTE algorithm has demonstrated significant improvements in accuracy when compared with several state-of-the-art algorithms, achieving roll angle error of ±0.4° and pitch angle error of ±0.2°.

Reconfigurable intelligent surface (RIS) has the potential to revolutionize wireless communications by dynamically controlling wireless channels to boost spectral efficiency (SE) and energy efficiency (EE), towards meeting the advanced specifications of Internet of Things (IoT) networks. In this context, we study the downlink harvested energy (HE), uplink SE and total EE of the RIS-aided cell-free massive multiple-input multiple-output (CF-mMIMO) system with wireless power transfer (WPT) technology. IoT devices harvest energy from the energy signals transmitted from access points (APs) during the downlink and use it for the uplink pilot and data transmission. Based on the unique characteristics of the channel fading model and the RIS deployment location, we put forward a novel RIS phase shift design scheme according to the line-of-sight (LoS) components of channels and verify its effectiveness. Furthermore, we derive the average HE and uplink SE in closed form with a two-layer decoding method (i.e., the maximal ratio combining (MRC) at APs is called first-layer decoding and the large-scale fading decoding (LSFD) at CPU is called second-layer decoding.) under the assumptions of both perfect and imperfect statistical channel state information (CSI). The results verify the derived closed-form expressions by Monte-Carlo simulations. Increasing the number of RIS elements further improves the uplink SE and total EE with the two-layer decoding. Since the statistical CSI is unknown in practical scenarios, we propose an acquisition method for the statistical CSI applicable to this system. Simulation results validate the efficiency of the proposed statistical CSI acquisition method. Furthermore, it is interesting to find that better statistical CSI estimation can be achieved with more coherent blocks of pilot.

Speech recognition serves as the foundation for human-computer interaction. To attain more accurate speech recognition results, the models for speech recognition are becoming increasingly sophisticated, demanding a greater volume of training data. In situations where data and computational resources are limited, the rapid development of usable speech recognition models becomes crucial for the future of this field. Currently, mainstream speech recognition models rely on attention mechanisms. These models employ cross-attention during decoding to address the relationship between the encoded speech input and the textual representation of the output. This mechanism allows the model to focus on different parts of one sequence while generating elements of another sequence, facilitating a better understanding of their relationships. However, stacking numerous layers of cross-attention is required to increase the model's expressive power. Yet, too many layers can impact model training and inference speed, and necessitate more data for training. We introduce a dynamic attention fusion speech recognition decoder designed for small datasets to address this issue. The decoder utilizes enhanced positional information during the decoding process to query the positional correspondence between the output text and the input speech encoding. This approach eliminates the need for extensive stacking of cross-attention mechanisms. Subsequently, a dynamic fusion module integrates these correspondences with the original decoding information. This method effectively establishes improved correspondences between the input and output, eliminating the need for stacking additional decoder layers and thereby reducing the model's parameter count. Our model achieved Character Error Rates (CER) of 4.60%, 12.67%, and 7.06% on the Aishell1, Primewords, and Free ST Chinese Mandarin Corpus datasets, respectively. Meanwhile, on the Uyghur dataset, our model attained a Word Error Rate (WER) of 4.23%. These results outperformed the baseline systems. The error rates decreased by 0.05%, 0.23%, 0.21%, and 1.52% on four datasets respectively compared to the baseline system. Additionally, our model's parameter count also decreased by 6.7%.

This paper presents a reconfigurable 4.75-to-32 GBuad transmitter (TX) that operates up to 64Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 32Gb/s with non-return-to-zero (NRZ) modulation scheme, designed in the 28-nm CMOS technology. The TX incorporates a quarter-rate architecture with a tap coefficient flexible feed-forward equalizer (FFE) up to 3 FFE taps. The TX employs a tailless CML driver with common-mode feedback (CMFB) for output swing control which provides 0.8 V pp output swing, and a helical wiring T -coil for bandwidth expansion. The clock path of the TX includes the duty-cycle detection/correction (DCD/DCC) circuits with a resolution of sub-60fs and quadrature-error detection/correction (QED/QEC) circuits, and a LC phase locked loop (PLL) with a local injection-locked (IL) quadrature clock generation circuit. The TX operating at 64 Gb/s in PAM-4 modulation consumes 76.7 mW from 1-V supply with 0.8 V pp, achieving an 1.2 pJ/b energy efficiency. The TX front end occupies an active area of 0.063 mm2.