Structural Health Monitoring (SHM) uses pervasive sensors to monitor the health and integrity of buildings and civil infrastructure, significantly reducing maintenance costs and improving safety. Despite its potential, widespread adoption of SHM is hindered by high deployment costs and privacy concerns from building tenants. This work introduces IceSpy as one solution to both problems: reducing the cost and improving the privacy of SHM applications. IceSpy uses a programmable multi-chip systolic array of small, low-power Commercial off-the Shelf (COTS) FPGAs to implement data filtering and differential privacy. Data filtering reduces cost by reducing power-hungry wireless data transmission, leading to smaller batteries and power harvesters. Meanwhile, local differential privacy removes privacy-sensitive information before transmitting it to an untrusted server. Even with additional differential privacy measures, IceSpy achieves a 3× reduction of power consumption and a consequent reduction in battery costs due to decreased wireless communication. This low-power privacy-preserving filtering technology reduces deployment costs and mitigates privacy concerns from potential deployment sites. With many obstacles removed, we are working on deploying IceSpy in dams and commercial buildings to obtain deeper insight into the structural health of buildings and infrastructure.

Wildfires are one of the most catastrophic natural disasters, causing increasingly severe ecological and economic damage. Early response is critically important for wildfire management, but also difficult due to the wide geographical area to monitor, often far from utility infrastructures such as stable power and high-bandwidth network. In this work, we present Xyloni, a very low-cost, low-power neural network accelerator for sensor nodes, which improves the cost-effectiveness and scalability of real-time wildfire detection by drastically reducing wireless data transmission and overall power consumption. Xyloni uses low-power flash and FeRAM memories to store a hardware co-optimized Neural Network model for fire and smoke detection, as well as intermediate activations during inference. It also time-shares a Field-Programmable Gate Array across different model layers for power-efficient computation. The detection model prevents benign images from consuming network traffic, allowing the use of low-bandwidth, low-power network fabrics such as a LoRa mesh network with enough range for the necessary geographical coverage. Compared to a wide range of edge and sensor platforms capable of real-time data collection, Xyloni demonstrated an order of magnitude reduction in power consumption for the network transmission reduction task, leading to a corresponding reduction in battery and deployment cost.

Emerging 3D memory technologies, such as the Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM), provide increased bandwidth and massive memory-level parallelism. Efficiently integrating emerging memories into existing system pose new challenges and require detailed evaluation in a real computing environment. In this paper, we propose MEG, an open-source, configurable, cycle-exact, and RISC-V based full system simulation infrastructure using FPGA and HMC. MEG has three highly configurable design components: (i) a HMC adaptation module that not only enables communication between the HMC device and the processor cores but also can be extended to fit other memories (e.g., HBM, nonvolatile memory) with minimal effort, (ii) a reconfigurable memory controller along with its OS support that can be effectively leveraged by system designers to perform software-hardware co-optimization, and (iii) a performance monitor module that effectively improves the observability and debuggability of the system to guide performance optimization. We provide a prototype implementation of MEG on Xilinx VCU110 board and demonstrate its capability, fidelity, and flexibility on real-world benchmark applications. We hope that our open-source release of MEG fills a gap in the space of publicly-available FPGA-based full system simulation infrastructures specifically targeting memory system and inspires further collaborative software/hardware innovations.