This article presents the design and miniaturization of a wideband monolithic microwave integrated circuit (MMIC) fully distributed efficient power amplifier (FDEPA). Distributed structure arrangement has been applied not only on the auxiliary power amplifier (PA) but also for the main PA. Hence, complicated and bandwidth-limited input matching networks (IMNs) and phase alignment networks are replaced by artificial transmission lines (ATMLs) to simplify the design and save the chip area. At the same time, due to the wide bandwidth characteristic of the distributed main PA, the power back-off (PBO) bandwidth shows good results compared with the conventional single common-source PA arrangement. Besides, a compact wideband on-chip quadrature hybrid power splitter is employed to achieve reasonable power division and phase control. As a proof of concept, an FDEPA prototype has been designed and fabricated in a commercial 0.25-μm GaN-on-SiC process. The chip size is only 3.6 mm×2.55 mm with all the necessary components. From the measurement results, throughout the working band of 3.1-5.5 GHz (56% fractional bandwidth), 40.3-41.6 dBm saturation output power (Psat), namely 1.16-1.58 W/mm2power density are achieved. The associated saturation drain efficiency (DE) is around 46%-55.4% and the 9-dB PBO DE is around 30.3%-47.2%. Under 100-MHz orthogonal frequency division multiplexing (OFDM) signal excitation with 8.5-dB peak-to-average power ratio (PAPR), 29.3%-44.5% average DE has been observed for the whole operating band, while the adjacent channel power ratio (ACPR) is better than -46.2 dBc with the digital pre-distortion (DPD).

This article presents an ultra-broadband distributed efficient power amplifier (DEPA) with reactance compensation and adaptive biasing. It is illustrated that the bandwidth of the DEPA can be improved apparently by applying a shunt short-circuited stub at the combining point. The principle of such method is that the back-off impedance variation with frequency can be compensated by the reactance of the shunt stub. Besides, to get over the high gain compression of the conventional DEPA, an adaptive biasing scheme is proposed for the auxiliary PAs. A DEPA is implemented in a 0.25-$\mu \text{m}$GaN-HEMT process for validation. The shunt stub is realized by a LC tank equivalently for a compact size. The fabricated DEPA achieves a saturated output power of 41.5–43 dBm and an 8-dB back-off drain efficiency (DE) of 38%–46.8% from 1.8 to 5.4 GHz with a chip size of$3.2\times3.2$mm2. The fractional bandwidth (FBW) is up to 100%. Applying a 100-MHz LTE signal with an 8.5-dB peak-to-average power ratio (PAPR), an average DE of 35%–43% is measured over the entire bandwidth, and adjacent channel power ratio (ACPR) is better than −47 dBc after applying digital predistortion. To the best of our knowledge, the proposed DEPA demonstrates the largest FBW among all reported integrated back-off efficient PAs without using digital techniques or reconfiguration.

In this article, a fully integrated 1.0–11.0-GHz wideband distributed power amplifier (DPA) monolithic microwave integrated circuit (MMIC) design is presented. Particularly, a coupled technique with bandpass (CTB) characteristic between the kth output node and the ($k+1$)th input node of amplification units (AUs) is adopted in the DPA design. It generates an additional signal reuse path (SRP) to reuse part of the output signal to superimpose the input signal, and then they will be reamplified to the output artificial transmission line (O-ATML). Moreover, due to the bandpass characteristic, the signal reuse can be manipulated to target the upper cutting edges of the working band to alleviate sharp gain and power roll-off. By carefully controlling the SRP, the overall gain, output power, and bandwidth are enhanced and extended. The systematic design approach for the DPA is detailed with circuit implementations and optimizations. To validate the proposed concept, a DPA MMIC prototype is implemented and fabricated in a commercial 0.25-$\mu $m gallium nitride (GaN)-on-silicon carbide (SiC) high-electron-mobility transistor (HEMT) process. It shows the compact layout within a die size of 3.36 mm2. Under 28-V VDD power supply, the measured results show a flat$14.8\pm 1.0$-dB small-signal gain with 10.0-GHz wide operating bandwidth and good impedance matching conditions. A saturated output power (${P} _{\text {sat}}$) of 7.25 W with peak power-added efficiency (PAE) exceeding 38.7% is achieved. The proposed DPA obtains around 1.54–2.16-W/mm2 power density associated with an average PAE of 34.5% over the entire frequency range.

Highly efficient power amplifiers (PAs) and associated linearization techniques have been developed to accommodate the explosive growth in the data transmission rate and application of massive multiple input multiple output (mMIMO) systems. In this paper, energy-efficient integrated Doherty PA monolithic microwave integrated circuits (MMICs) and linearization techniques are reviewed for both the sub-6 GHz and millimeter-wave (mm-Wave) fifth-generation (5G) mMIMO systems; different semiconductor processes and architectures are compared and analyzed. Since the 5G protocols have not yet been finalized and PA specifications for mMIMO are still under consideration, it is worth investigating novel design methods to further improve their efficiency and linearity performance. Digital predistortion techniques need to evolve to be adapted in mMIMO systems, and some creative linearity enhancement techniques are needed to simultaneously improve the compensation accuracy and reduce the power consumption.