As AI and its applications evolve, efficient hardware is required to run the novel algorithms. Compute platforms with a high degree of parallelism, such as matrix-vector multipliers, meet the need to process large homogeneous loads of operations. However, most of the matrix-vector multiplications required by the AI algorithms are larger than what the actual hardware supports. The operations must therefore be tiled into blocks that fit on the given hardware. Finally, the partial sums generated by the hardware for each tile must be accumulated or concatenated into the complete result. Especially with mixed-signal compute-in-memory architectures, this can lead to quantization on two levels. First, an ADC quantizes the partial sums generated for each tile. Then, the algorithm performs another quantization of the final result to limit bitwidth and resource consumption in adjacent computations. While quantizing only the partial sums or only the final results has been studied extensively, the combination of the two has yet to be investigated. This work introduces a simulator to understand the effects of quantization caused by multiple quantization steps on different levels. It is based on a generic, stochastic representation of value probabilities using histograms. Common operations such as scaling, rounding, and accumulation are implemented in this representation, allowing the effect of quantization to be studied in a matrix-vector-multiplier application. It is shown, that the selection of tilesize, ADC bitwidth and clipping technique form a complex trade-off, which can be solved using PSumSim. PSumSim is available under https://github.com/Joschua-Conrad/PSumSim.

This work links Ring Oscillator (RO)-Physical Unclonable Function (PUF) specific design parameters with previously neglected area consumption per PUF bit. In prior art, the PUF specific design parameters such as number of ROs in a given RO collection that can be compared to one another and readout time are optimised in terms of e.g stability and/or power consumption. The influence of these design parameters on the effectively required area per bit remains overlooked, since optimization on area is mostly done simply by designing small ROs. This work establishes a relationship between the general design parameters and the area per bit for RO-PUFs. Using finite frequency readout resolution by means of a limited readout time, the RO-PUF is transformed into graph-theory and by finding a Minimum Spanning Tree (MST), the best possible yield of a given collection of ROs is determined. The given collection together with variable yield is then mapped to a certain demand on area per bit. An extensive yield analysis is performed which then is again mapped to a certain area per bit, leading to the proposed connection between readout time, amount of ROs in a collection and area per bit.The system-level analysis performed shows that a set of 8 ROs represents a sweet-spot in terms of area per bit as well as low read-out time.

A well-known problem when using Physical Unclonable Functions for secret key generation and storage, is the instability of PUF responses due to environmental conditions like temperature variations. Using Ring Oscillator PUFs (RO-PUFs), a response bit is usually derived based on the comparison of a RO frequency with either a threshold or another RO frequency. Especially for multi-valued PUFs it is of importance to decrease RO frequency errors before digitization. Otherwise, these errors can result in a huge amount of bit-flips. To counteract environmental influence in the reproduction phase, we propose to map a frequency, which might be remeasured under a temperature condition different from initialization, closer to the initial frequency by using a method based on polynomial interpolation. This paper presents how such an approach can decrease errors in multi-valued responses and evaluates the error based on the used polynomial order and thus complexity.

Physical unclonable functions (PUFs) produce responses by exploiting randomness that intrinsically occurs in integrated circuits due to uncontrollable variations in the manufacturing process of physical items. It is common practice that PUFs generate binary responses. Recently, it has been proposed to extract symbols from a higher-order alphabet in order to increase the length of the final response. In this paper, coding for this concept of multi-valued PUFs (MV-PUFs) is derived from the analogy to pulse-amplitude modulation in digital communications. To that end, based on ROPUF measurement data, we replace the classical binary symmetric channel model by a suited additive white Gaussian noise model. Consequently, the hard-input binary channel coding scheme is replaced by methods from coded modulation, utilizing the soft output. In addition, the functionality of helper data, which are required to stabilize noisy PUF responses, is transferred to the multi-valued case. By applying the designed methods to the available measurement data we eventually show that imagining the analog PUF output as$M$-ary amplitude-shift keying symbols observed over an AWGN channel, both the extracted entropy per response symbol and the reliability of the final key can be increased.

This demo shows the automated characterization of Xilinx Zynq FPGAs on the Digilent Zybo with the help of a framework based on Partial Reconfiguration. Fine-granular measurements of the whole chip area reveals several aspects which have to be taken into account for PUF system design on these devices. In this demo, the visitor will get to know the general measurement approach and explanations about the provided results. With the help of a python based tool, the visitor can experience the workflow first-hand, generate their own measurements and use them to differentiate a single board from a set of multiple other boards. Further in-sight can be gained by analysis of the different statistical metrics and by combining measurements from multiple boards.

Physical Unclonable Functions utilize random variations from manufacturing to generate unpredictable, yet repeat-able fingerprints of devices for usage in a hardware cryptographic context. Most often, they are dedicated electrical circuits in integrated devices and thus occupy additional space while only few implementations exploiting already existing hardware. In this work, we analyze the possibility to extract hardware unique fingerprints from the distinct differential nonlinearities of analog-to-digital converters, which are present in almost every system. The transfer curves from measuring a large set of low-cost analog-to-digital converters with 12 bit resolution are analyzed regarding their quality as system fingerprints. Additional postprocessing methods are investigated for further improvement of the uniqueness metrics. The fingerprints are optimized to a perfect inter-hamming distance of 50% and close-to-maximum entropy. These improvements come at the cost of a reduced number of extracted bits, yet the minimum achieved number of 440 bits is sufficient for secret key generation. By thresholding and consequently avoiding unstable positions in the extracted bit-strings, the intra-hamming distance of unprocessed transfer curves could be reduced to less than 4%. Further measurements over a large temperature range shows that the error rate due to temperature drift never exceeds 13%.

Physical unclonable functions are integrated circuits well-known for their potential to replace dedicated secure storage of cryptographic keys. On FGPAs, ring-oscillators have received great attention as the most preferable implementation. Many measurement data sets have been published with large quantities of ring-oscillators on large quantities of chips. Yet, all these data sets are missing large quantities of readouts, which limits their usage for proving the efficiency of error correction algorithms. In this work, we present multiple different approaches of measurement control and readout extraction for external storage. We cover the full development process, beginning with slow extraction in early stages for maximum control up to final extraction with automated high-speed designs. Targeting a Zynq-7000 architecture, the final design extracts 3800 · 10000 readouts within 8.04 s, which relates to a data extraction rate of 36 Mbit/s. In comparison to an early stage design, which took 452.91s for the same measurement, a reduction in total run time of 98.2% was achieved.

Bandpass ΣΔ modulators using LC resonators typically require an active Q-enhancement circuit in order to achieve a higher resolution. However, the Q-enhancement circuit operating at GHz range suffers from finite speed due to power constraints. In this paper, the effects of finite gain-bandwidth of the Q-enhancement circuit in bandpass ΣΔ modulators are analyzed, and a mathematical model is derived. The model quantitatively clarifies the two kinds of distortion in the noise transfer function due to finite gain-bandwidth, namely a shift of the in-band zeros and an out-of-band peaking. Compensation is then applied such that the original noise shaping is retained. Consequently, Q-enhancement circuit can be designed with a smaller gain-bandwidth in order to reduce its power consumption.

Physical Unclonable Functions (PUFs) offer the possibility to produce unique fingerprints for integrated circuits. As raw PUF responses are affected by noise, some post-processing steps are necessary. We present a coding chain test framework for PUFs on Field Programmable Gate Arrays. The framework allows easy exchange, evaluation and comparison of different PUF implementations, coding algorithms and other chain modules. For a testing framework, the execution time of the evaluated algorithm is a bottleneck, since a huge amount of runs are supposed to be done. Hence, we additionally present a new type of Reed-Muller decoder hardware architecture using parallel modules to speed up the decoding process. The decoding time could be decreased by 95% in comparison to existing implementations at the cost of 41 times higher slice count.

Electrical Impedance Spectroscopy (EIS) is a popular method for investigating tissue properties. Implementing the signal generator for EIS measurements with a suitable excitation signal type is thereby one of the two system components. The choice of the excitation signal defines the measurement speed, signal-to-noise ratio (SNR), total area and power consumption of the system, and many more properties. Signal types such as analog single-tone, analog multi-tone, linear feedback shift registers (LFSR), and single-tone Sigma Delta Modulated (ΣΔM) are proposed in the state of the art. In this work an EIS setup is implemented and successfully tested with all the mentioned signal types to evaluate their properties on impedance models as well as in vitro cell layers. It is proposed to combine the ΣΔM with the multi-tone excitation signal yielding a very versatile excitation generator. Multi-tone ΣΔM are as fast as analog multi-tones, while benefiting from a binary output and thus less system complexity. The implemented EIS setup is used to perform EIS measurement for biological samples. The results show a very good matching with the reference for all the excitation signals.