This brief presents an energy-efficient design with cascaded structure aiming at multiclass heartbeat classification. support vector machine-based granular resampling method is put forward to obtain a hybrid classifier which includes a low-complexity model (LCM) to identify most easy-to-learn heartbeats and a high-accuracy classifier to discriminate the remained. The hybrid classifier combined with one-versus-all strategy is employed to achieve a multiclass classification model. An adaptive speculative mechanism based on the occurrence regularity of electrocardiogram abnormities is proposed to lower the complexity and computation burden of the multiclass classification model. The corresponding energy-efficient hardware architecture is designed and its architecture optimizations include memory segmentation to reduce energy consumption and time domain reuse to save resources. Implemented in 40-nm CMOS process, the design occupies 0.135 mm2area. It consumes 2.60-48.99 nJ/classification under 1-V voltage supply and 1 MHz operating frequency. Results show that the design provides an average prediction speedup by 60.66% and a significant energy dissipation reduction by 55.26% per beat compared with a high-accuracy model without LCMs.

Recurrent neural networks (RNNs) perform excellently on sequencing tasks but are severely restricted by the complex computations and intensive memory consumption due to their internal fully connected topologies, thereby making it a great challenge to implement RNNs on embedded devices. In this brief, we propose an energy-efficient RNN processor by exploiting the data locality in network compression using an innovative quantified sparse matrix encoding format. Compared with the conventional processors for compressed RNNs, more than 80% of the weight fetching and matrix-vector multiplications can be further reduced in applications, such as natural language and keyword spotting. To handle different scales of RNN models without introducing significant interactive overhead, scalable hardware architecture is presented to organize multiple processor engines in a spatial fashion with the assistance of the network cross-division strategy. Synthesized in the SMIC 40LL CMOS process, the prototype processor has a total area of 0.65 mm2with 95.5 kB of static random-access memory capacity. Based on the simulation, this processor achieves a peak performance of 24 GOPS and dissipates 6.16-mW power with 1.1 V supply and 200 MHz. The peak energy efficiency reaches 3.89 GOPS/mW, which is state of the art among existing RNN accelerators.