Since dynamic power has a quadratic relationship with voltage, reducing voltage is an effective way to lower power consumption in digital circuits. However, maintaining stable operation at lower voltages is challenging due to increased sensitivity to Process, Voltage, and Temperature (PVT) variations, making it difficult to determine optimal operating points using Static Timing Analysis (STA). While circuit-and device-level solutions like Timing Error Detection (TED) systems can enable lower voltage operation, they introduce significant overhead and design complexity. In this paper, we integrate an Algorithm-Based Fault Detection (ABFT) method into the structure of systolic arrays to capture timing errors when voltage is scaled down, ensuring safe and optimized low-voltage operation. Our proposed approach, SCISSORS, demonstrates how extra voltage margins in systolic arrays used for matrix arithmetic can be trimmed by integrating a simple algorithmic technique into the structure of the array. This solution not only detects errors in the accelerator but also those caused by voltage reduction in on-chip memory and auxiliary circuits. It is fully implementable through HDL without requiring transistor-or circuit-level modifications to the netlist. Implementation on a Zynq System-on-Chip (SoC) shows that SCISSORS introduces only a tolerable overhead of 11% and 8% for 32×32 and 64×64 systolic arrays, respectively, while achieving nearly a 2× improvement in energy efficiency. Experimental results further demonstrate that SCISSORS adaptively adjusts voltage in response to the voltage-temperature coupling behavior of digital circuits at runtime, specifically addressing Inverse Temperature Dependence (ITD).

Coarse-Grained Reconfigurable Architectures (CGRAs) are one of the promising solutions to be employed in power-hungry edge devices owing to providing a good balance between reconfigurability, performance and energy-efficiency. Most of the proposed CGRAs feature a homogeneous set of processing elements (PEs) which all support the same set of operations. Homogeneous PEs can lead to high unwanted power consumption. As application benchmarks utilize different operations irregularly, heterogeneous PE design is a powerful approach to reduce power consumption of CGRA. In this paper, we propose DA-CGRA, a domain-aware CGRA tailored to signal processing applications. To extract heterogeneous architecture, first, a set of signal processing applications has been profiled to derive the requirements of the applications in terms of type of operations, number of operations and memory usage. Then, domain-specific PEs are designed using Verilog RTL based on the profiling results. We have selected spatio-temporal or spatial execution model based on the application features to increase the overall performance and efficiency. Experimental results demonstrate DA-CGRA outperforms FLEX and RipTide state-of-the-art CGRAs in terms of energy-efficiency by 23% and 38%, respectively. Moreover, DA-CGRA can achieve 3.2x performance improvement over HM-HvCUBE.

Coarse-Grained Reconfigurable Architectures (CGRAs) are promising solutions to achieve more performance with the end of Moore's law. CGRAs can provide flexibility as well as near-ASIC energy efficiency. Since the advent of IoT and battery-powered edge devices, energy efficiency is becoming increasingly important. Memory accesses contribute to about 50% of overall energy consumption of the CGRAs. Interesting features of emerging non-volatile memories (eNVMs) like low power consumption and high density have grown the attentions. In this work, the effect of eNVMs on energy efficiency of CGRAs have been investigated. The analysis using Polybench benchmark suite shows that STT-MRAM and PCM can result in a 94 % and 85 % reduction of energy consumption of memory accesses respectively compared to SRAM. Moreover, total access latency can also be improved by 60% and 49% in STT-MRAM and PCM.

Coarse-Grained Reconfigurable Architectures (CGRAs) are promising solutions to achieve more performance with the end of Moore's law. Thanks to word-level programmability, they are more energy-efficient compared to FPGAs. Although ASICs can minimize energy, they suffer from high Non-Recurring Engineering (NRE) costs and inflexibility. CGRAs provide near ASIC energy efficiency and are deployed in the literature to accelerate low-power and high-performance applications. However, focusing on low-power CGRAs is crucial as a high volume of data should be processed on a resource-constrained device by the development of IoT and Machine Learning applications. This survey has reviewed and categorized CGRA architectures from processing elements, interconnect networks, and memory points of view and derived guidelines for energy-efficient CGRA design.