The globalization of the integrated circuit supply chain has introduced untrustworthy entities at various stages, arousing increasing attention to hardware security research from both academia and industry. Some tasks in hardware security research require matching two hardware designs. For example, in gate-level netlist reverse engineering, after recovering module boundaries and hierarchical structure from a netlist, one must match each candidate module against known library components to validate its functionality. Likewise, in Intellectual Property (IP) piracy detection, a suspected infringing IP can be matched against its original counterpart to determine whether infringement has occurred. We design and implement a hardware similarity evaluation framework called Twins. We develop two versions of the framework, called Twins-v1 with the basic Graph Neural Network (GNN) model and Twins-v2 with the node-independent GNN model, respectively. Twins employs a more effective training approach that substantially reduces training time and improves evaluation metrics compared to the current state-of-the-art models. Furthermore, to the best of our knowledge, Twins-v2 represents the first work to use independent graph convolutional network layers based on different node types in the context of hardware security research. The novel netlist graph extraction method has also been experimentally demonstrated to outperform the previously employed data flow graph approach in hardware similarity evaluation tasks. After conducting experimental evaluations on a dataset comprising 305 circuits, both Twins-v1 and Twins-v2 significantly surpass existing methods in terms of prediction accuracy and efficiency.

Advancements in technology have led to a continuous reduction in the size of transistors and an increase in the complexity of circuits, posing significant challenges for Electronic Design Automation (EDA) tools. Concurrently, the rapid growth of deep learning has extended its reach across various domains, yielding promising outcomes. Particularly with large-scale datasets, deep learning techniques often demonstrate superior efficiency. Circuits exhibit diverse graph structures spanning from Register-Transfer Level (RTL) to gate-level netlist representations, including Data Flow Graph (DFG), And-Inverter Graph (AIG), and mapped netlist graph, which align well with graph neural networks. Leveraging various open-source tools, GNN4HHR amalgamates disparate graphs from multiple stages into a hybrid hardware representation. The GNN model can effectively distinguish and encode circuits at various stages.

The detection of patch presence test plays a crucial role in preventing 1-day vulnerability exploitation. Current approaches however face significant challenges in cross-architecture scenarios due to compiler optimization variations and code obfuscation techniques, manifesting in elevated false positive rates and limited generalization. This paper presents MR-Patch, a Multimodal Retrieval-Augmented Patch Verification system that synergizes static analysis with large language model capabilities. The framework employs context-sensitive basic block signature mapping to isolate security-relevant code regions, constructing enriched semantic representations through the joint modeling of control flow graphs, data flow graphs, and instruction-level semantics. A heterogeneous-aware embedding model dynamically fuses these tri-modal features using an adaptive weight allocation mechanism that resists compilation induced distortions. The system’s innovation lies in its hierarchical verification architecture: initial similarity matching via multimodal retrieval is augmented by a locally deployed expert LLM performing contextual semantic validation.Experimental results demonstrate that MR-Patch attains an accuracy of 89.1 % on a test set comprising 6,980 cross-version functions, thereby validating the efficacy of large language models in patch detection.

As the integrated circuit (IC) supply chain globalizes, fabrication, testing and packaging are outsourced to third-party entities, and intellectual property (IP) is widely used. As a result, new hardware security threats, including IP piracy, have emerged. Graph similarity learning is a promising technique for estimating the similarity between two input graphs and can be used to detect IP piracy after modeling input hardware designs as graphs. In this work, we propose a hardware similarity learning framework, HWSim, for gate-level IP piracy detection. We transform the gate-level netlists to directed graphs and encode graphs using the graph neural network (GNN) model which is trained based on metric learning. We optimize the training process and use a negative mining strategy to improve training efficiency. HWSim can be trained in a much shorter time compared to the baseline method and achieves an AUC score of 0.9963 on our dataset collected from open source benchmarks.