Balanced ternary digital logic circuits based on memristors and MOSFET devices are introduced. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are designed and verified by simulation. Next, logic circuits such as ternary encoders, decoders and multiplexers are designed using these three basic gates. For further validation, a ternary 3–1 encoder was hardware-implemented successfully using in-house fabricated memristors and MOS transistors. Two different design approaches, namely the decoder-based method and the multiplexer-based method are introduced and applied to realize combinational logic circuits such as balanced ternary half-adder, multiplier, and numerical comparator. We simulate the circuits using 50nm CMOS technology parameters and BSIM models and present comparisons and analyses of the two design methods in view of the power consumption and component device counts, which can guide subsequent research and development of integrated multi-valued logic circuits. The decoder-based method has advantages both in terms of component numbers and power consumption, but the multiplexer-based method has the advantages of being based on a simple operating principle and ease of implementation.

Locally-active memristor (LAM) is one of the promising candidates of artificial neurons, indicating it has potential applications in neuromorphic computing. Quantitative theoretical analysis on LAMs can provide benefits for designing related oscillator circuits and systems. This study begins with the aim of assessing the importance of DCV-Icharacteristic in the performance of LAMs by using small-signal analysis method. The DCV-Icurve of the LAM is specified by two parameters involving resistance (conductance) and differential resistance (differential conductance). In addition to these two static parameters, we extract a crucial dynamic parameter to describe the behavior of the LAM. Theoretical analysis demonstrates that the performance of generic current-controlled and voltage-controlled LAMs is closely associated with three crucial parameters, i.e., the above two static and one dynamic parameters. Hence, only based on these three parameters, can one derive the small-signal equivalent circuit of LAMs and determine the oscillation frequency range and condition for simple LAM-based oscillators. By applying the presented universal dynamics analysis results, we further propose a modified mathematical model with higher accuracy to mimic the quasi-static and oscillating behaviors of a real Nb2O5device, and provide some fundamental guidance for the design of LAM-based high-frequency oscillators.

This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the variety of challenges that affect device performance. Noise accumulation across subsequent stages can be amortized by integrating ternary logic gates, thus enabling higher density data transmission, where more complex computation can take place within a smaller number of stages when compared to single-bit computation. We present the design of a ternary half adder, a ternary full adder, a ternary multiplier, and a ternary magnitude comparator. These designs are simulated in SPICE using the broadly accessible Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfOxmemristor which exhibits low cycle-to-cycle variation, and thus contributes to robust long-term performance. We ultimately show an improvement in data density in each logic block of between$5.2\times - 17.3\times $, which also accounts for intermediate voltage buffering to alleviate the memristive loading problem.