This paper presents a$200\times 232$CMOS indirect time-of-flight (iToF) sensor with an adaptive multiple sampling scheme that adjusts the number of samplings depending on the signal level for suppressing depth noise. A 10-b column-parallel single-slope analog-to-digital converter (SS-ADC) with five folded ramps is proposed to improve signal quality in the digital domain by sampling pixel voltages multiple times. The appropriate ramp is selected based on the signal level, and the optimal number of samplings is proceeded, enhancing overall efficiency. As the number of folding in the ramps is doubled in consecutive order while the range of the subsequent ramp is half of the previous one, the conversion time of the proposed SS-ADC is constant regardless of the ramp choice. In addition, the sensor incorporates an on-chip foreground calibration to mitigate the nonlinearity stemming from the mismatch of multiple ramps. The calibration is achieved by modifying the capacitance of the ramp generators. The prototype iToF sensor fabricated in a 110 nm BSI process achieves depth images from 0.6 m to 6.0 m with a high depth precision of 0.72% at 25 MHz modulation frequency and 60 fps without any frame rate degradation. The foreground calibration is successfully demonstrated by improving DNL errors smaller than ±0.7 LSB.

A CMOS indirect time-of-flight (iToF) sensor with a multiple sampling scheme for suppressing depth noise is presented. A 10-b column-parallel single-slope analog-to-digital converter (SS-ADC) with five folded ramps is proposed to sample pixel voltages several times, improving signal quality in the digital domain. A conversion time is constant regardless of the ramps because the number of folding in the ramps is dependent on the signal level. In addition, a foreground calibration for matching the ramp slopes is conducted on a chip, enhancing linearity. The prototype iToF sensor fabricated in a 110-nm BSI process achieves a high depth precision of 0.72% from 0.6 m to 6.0 m at 25 MHz modulation frequency.

Multiscale dynamics of neural and metabolic interactions implicated in disease states call for precision electrophysiology to resolve a variety of biopotential signals across the body that cover a wide range of frequencies, from the mHz-range electrogastrogram (EGG) to the kHz-range electroneurogram (ENG). Currently available integrated systems for unobtrusive and minimally invasive electrophysiology suffer from tradeoffs between bandwidth coverage, noise floor, power consumption, and input impedance, which limits their detection range and accuracy. Here we present a 16-channel wide-band ultra-low-noise neural recording system-on-chip fabricated in 65nm CMOS for chronic use in mobile healthcare settings that covers 0.001 Hz to 1 kHz bandwidth through sample-level duty-cycling. Each channel consists of a delta-sigma analog-to-digital converter (ADC) achieving$\mathbf{1.0}\ \mu \mathbf{V}_{rms}$input-referred noise over 1 Hz - 1 kHz bandwidth with a Noise Efficiency Factor (NEF) of 2.93 in continuous operation mode, while power duty-cycling of the biasing and clocks maintains consistent low input-referred noise levels down to 0.001 Hz sampling rates at$\mathbf{435}\ \mathbf{M}\Omega$input impedance. In vivo recordings from the chip interfacing to electrodes mounted on the forehead resolving slow-wave electroencephalogram (EEG) biopotentials demonstrate proof-of-concept functionality.