Assessment management in large‑enrollment microelectronics laboratory courses places a substantial administrative burden on graduate teaching assistants (GTAs), who must aggregate scores across multipart deliverables, apply class‑wide curves, roll extra credit into summative grades, enforce score caps, and post results to the Learning Management System (LMS). The prevailing approach exporting a gradebook CSV from Canvas, editing it in a spreadsheet, and re‑importing is serial, introduces manual transcription steps well documented to produce errors, and offers no guarantee against silent data loss caused by Canvas’s fragile column‑matching import rules. We present Score‑Reflow, a Python‑based GUI that communicates directly with the Canvas LMS REST API, replacing the CSV loop with a single‑click, auditable pipeline, while also significantly improving grading accuracy and traceability for large courses. Score‑Reflow implements a generalized bounded‑additivity model that subsumes five assessment‑workflow patterns common in hardware labs: (1) uniform class curve, (2) extra‑credit roll‑up, (3) multipart aggregation, (4) bounded curve‑and‑cap, and (5) cross‑name-space resolution of Canvas quiz and assignment identifiers. Deployed in a required four‑credit ECE course serving 175 students across six lab sections, Score‑Reflow reduces a multi‑hour grading event to minutes, enforces consistent treatment across sections, and returns GTA time to direct instructional engagement that advances laboratory learning outcomes.

Professional success in STEM fields extends beyond technical expertise, requiring strong communication and teamwork skills. While program accreditation agencies emphasize these competencies, traditional classroom methods focus heavily on individual learning, offering limited collaboration opportunities. Digital learning platforms enhance engagement but often lack real-time peer interaction and teamwork. In this work, we present PeerCollate - a scalable, technology-enhanced learning strategy to promote active learning and peer collaboration in STEM curricula within both traditional and hybrid instruction modalities. PeerCollate integrates open-source electronic collaboration tools with Learning Management Systems (LMS) to facilitate structured teamwork, enabling students to engage in problem-solving activities through virtual team-based learning. For instructors, this approach supports dynamic assessment and real-time feedback, improving student engagement and learning outcomes. Additionally, a digitally mediated post-examination remediation method is introduced, where students are grouped based on differing knowledge gaps to encourage peer-assisted learning. Through this collaborative approach, students refine their understanding before meeting with teaching assistants for further clarification and potential opportunity for score adjustments. By fostering teamwork, enhancing problem-solving abilities, and streamlining assessment, this model significantly improves the effectiveness and scalability of STEM education.

There is significant demand and urgency to prepare electrical and computer engineering students regarding the operational and performance characteristics of machine learning (ML) hardware accelerators. Convolutional Neural Networks (CNNs), which are utilized for real-time and large dataset image classification tasks, are appropriate targets for hardware acceleration. Designing accelerators for CNNs necessitates understanding the manipulation of CNN parameters. We introduce a hands-on pedagogy whereby learners can identify, modify, and appreciate the interaction of the CNN parameters within an interactive GUI. CASCADE (Computer Aided Student's CNN Analyzer for Design Exploration), a simulation-based framework for Design Space Exploration (DSE) of CNN FPGA-based accelerators is developed, including datapath synthesis, simulation, training, and testbench steps. We offer a case study of High-Level Synthesis (HLS) based CNN implementations targeting the MNIST dataset and present simulation results, namely hardware utilization, accuracy, and operating frequency, and offer insight into potential design trade-offs facing modern engineers.

Neural networks offer viable alternatives for energy versus accuracy tradeoffs, in particular with regards to the precision of the computational circuit. This paper explores use of progressive modular redundancy of intrinsically low energy, low precision circuits as an alternative to more complex networks yielding higher accuracy directly. Results indicate that a lower footprint temporal modular redundancy, which is applied progressively as needed, can have lower footprint and reduced energy consumption at comparable or slightly reduced accuracy as more complex neural networks. This provides an alternative to binarization and other model compression options for intelligence at the edge of the network. Our Progressive Modular Redundancy approach using varied activations implemented using a$\mathbf{784}\times \mathbf{100}\times \mathbf{10}$network shows a 3% improvement in accuracy compared to the baseline case of$\mathbf{784}\times \mathbf{500}\times \mathbf{500}\times \mathbf{10}$network with sigmoidal activation, at 86.1% and 87% reduction in power and weighted crossbar normalized area overhead, respectively, 87.5% reduction in power error product (PEP) at the cost of ~2.6x increased throughput latency.

Nowadays, from companies to academics, researchers across the world are interested in developing recurrent neural networks due to their incredible feats in various applications, such as speech recognition, video detection, predictions, and machine translation. However, the advantages of recurrent neural networks accompanied by high computational and power demands, which are a major design constraint for electronic devices with limited resources used in such network implementations. Optimizing the recurrent neural networks, such as model compression, is crucial to ensure the broad deployment of recurrent neural networks and promote recurrent neural networks for implementing most resource-constrained scenarios. Among many techniques, tensor train (TT) decomposition is considered an up-and-coming technology. Although our previous efforts have achieved 1) expanding limits of many multiplications within eliminating all redundant computations; and 2) decomposing into multi-stage processing to reduce memory traffic, this work still faces some limitations. In particular, current TT decomposition on recurrent neural networks leads to a complex computation sensitive to the quality of training datasets. In this paper, we investigate a new method for TT decomposition on recurrent neural networks for constructing an efficient model within imbalance datasets to overcome this issue. Experimental results show that the proposed new training method can achieve significant improvements in accuracy, precision, recall, F1-score, False Negative Rate (FNR), and False Omission Rate (FOR).

Sleep Convention Logic (SCL) is an emerging ultra-low power Quasi-Delay Insensitive (QDI) asynchronous design paradigm with enormous potential for industrial applications. Design validation is a critical concern before commercialization. Unlike other QDI paradigms, such as NULL Convention Logic (NCL) and Pre-Charge Half Buffers (PCHB), there exists no formal verification methods for SCL. In this paper, we propose a unified formal verification scheme for combinational as well as sequential SCL circuits, based on equivalence checking, which verifies both safety and liveness. The method is demonstrated using several multipliers, MACs, and ISCAS benchmarks.