In-memory computing (IMC) substantially improves the energy efficiency of deep neural network (DNNs) hardware by activating many rows together and performing analog computing. The noisy analog IMC induces some amount of accuracy drop in hardware acceleration, which is generally considered as a negative effect. However, in this work, we discover that such hardware intrinsic noise can, on the contrary, play a positive role in enhancing adversarial robustness. To achieve that, we propose a new DNN training scheme that integrates measured IMC hardware noise and aggressive partial sum quantization at the IMC crossbar. We show that this effectively improves the robustness of IMC DNN hardware against both adversarial input and weight attacks. Against black-box adversarial input attacks and bit-flip weight attacks, DNN robustness has improved by up to 10.5% (CFAR-10 accuracy) and 33.6% (number of bit-flips), respectively, compared to conventional DNNs.

In-memory computing (IMC) has been demonstrated as a promising technique to significantly improve energy-efficiency for deep neural network (DNN) hardware accelerators. However, designing one involves setting many design variables such as the number of parallel rows to assert, analog-to-digital converter (ADC) at the periphery of memory sub-array, activation/weight precisions of DNNs, etc., which affect energy-efficiency, DNN accuracy, and area. While individual IMC designs have been presented in the literature, they have not investigated this multi-dimensional design optimization. In this paper, to fill this knowledge gap, we present a SRAM-based IMC hardware modeling and optimization framework. A unified systematic study closely models IMC hardware, and investigates how a number of design variables and nonidealities (e.g. device mismatch and ADC quantization) affect the DNN accuracy of IMC design. To maintain high DNN accuracy for the IMC SRAM hardware, it is shown that the number of activated rows, ADC resolution, ADC quantization range, and different sources of variability/noise need to be carefully selected and co-optimized with an underlying DNN algorithm to implement.

For wearable devices that monitor personal health, secure access to private medical data becomes a crucial feature. Nowadays, device authentication based on biometrics such as fingerprint or iris has become increasingly popular. In this work, we investigate using electrocardiogram (ECG) signals as the biometric modality for device authentication, and we present accurate and low-power ECG-based authentication hardware. Deep neural networks (DNNs) have been employed with a cost function that maximizes inter-individual distance and minimizes intra-individual distance over time. During DNN training, we also introduce joint optimization of low-precision and structured sparsity, so that the real-time authentication hardware can consume minimal energy and area. Experimental results of custom hardware designed in 65nm LP CMOS technology exhibit low power consumption of 59.4 μW for real-time ECG authentication with a low equal error rate of 1.002% for a large 741-subject inhouse ECG database.