This article presents a novel data acquisition system (DAS) designed for area-sensitive applications, including automotive instrumentation, launch vehicles, and satellites, which require efficient area utilization and full-swing input/output capabilities for diverse sensors. Traditional approaches to achieving full swing, such as using CMOS input transistors or generating negative voltage via charge pumps, either result in high harmonic distortion (HD) or complicate chip design. To address these challenges, we propose a complementary analog front-end (CAFE) that shifts the input signal by a fixed voltage, enabling operation in a more linear region while employing feedback to minimize HD. The system incorporates two analog-to-digital converters (ADCs) that convert the input signal and subtract the digital output of the common mode voltage ($V_{\text {CM}}$), facilitating effective data fusion for complete AD conversion. Fabricated using a 180-nm 1P5M BCD process, the DAS consumes 118.81 mW from a 5.0-V power supply, providing 64 channels in a compact area of$4.0\times 3.2$mm. At a sampling rate of 1 MS/s, it achieves an effective number of bits (ENoBs) of 13.16, with a power consumption of 1.856 mW per channel and a dynamic range of 83.3 dB, resulting in an impressive figure of merit per channel (FoMS/Ch) of 165.3 dB.

This paper presents an uncooled infrared imager with flicker noise reduction, which is realized by the proposed phase difference modulation (PDM) method. The PDM method makes noise transfer function (NTF) generate a series of notches to reduce flicker noise. To realize PDM, a high-speed sub-frame readout circuit is proposed. The readout circuit has been manufactured and the output data is processed with FPGA. The measurement results show that the flicker noise power in the frequency range above 10Hz is reduced by 42% compared with traditional method at 60fps full image output rate, and the noise equivalent temperature difference (NETD) is reduced from 40mK to 34mK.

This paper presents a low-power readout circuit with 14-bit column-level extended-counting ADC for 17μm-pitch 1024 × 768 silicon diode uncooled infrared imagers. The ADC's coarse conversion adopts a current-mode DAC to feedback charge into a CTIA-based integrator during integration and the fine conversion is implemented by a SAR ADC after integration. A current self-compensator and a modified DAC are proposed to reduce more than 50% power of the overall integrator compared with conventional structure. The 1024 × 768 readout circuit has been fabricated in the 0.18 μm 1P5M CMOS process. Power consumption of the readout circuit is 104mW and each column ADC only consumes 15μW. Simulation results show that the RMS noise of the readout circuit is 0.9LSB and nonlinearity is 0.06% at 30fps.

This paper presents a 16-bit 64-channel 2-order incremental Σ-Δ ADC with an on-chip decimating filter for linear X-ray detector array. In order to achieve high-resolution and multi-channel integration, a series of coefficients for a 2-order Σ-Δ modulator are optimally designed which are based on time-domain relationship between the modulator input and output. Therefore, a decimating filter consists of only a counter and an integrator can be used to acquire Nyquist rate output. A residual error reduction method at the end of each conversion period is also proposed to refine the resolution of convertor by extending several clock cycles and reusing the same circuit modules. As a result, a high-resolution, small area cost and power efficient readout interface circuit (ROIC) is achieved. A prototype chip is designed in 0.18μm CMOS process. Simulation results reveal the ADC achieves ±0.5 LSB quantization error and 91.4 dB SNR within 1.9 kHz bandwidth, meanwhile, area of the decimating filter in single channel is only 42×90 μm2.