Physical Unclonable Function (PUF) emerges as a promising solution for Internet of Things (IoT) and hardware security systems. Nevertheless, the advancement in the design of IoT constrained devices is limited due to area overhead and power consumption incurred from applying complex and expensive methods to strengthen hardware security systems in particular the PUF. This paper leverages a reconfigurable PUF design as an efficient solution for hardware security of IoT constrained devices. This work proposes ERRO PUF as a novel economic improved-uniqueness reliable reconfigurable RO PUF for IoT and hardware security. ERRO PUF reduces area overhead and power consumption of the design, improves system design reusability, and reduces hardware resources utilization. It generates more CRPs with considerably less hardware resources, improves hardware efficiency of the PUF design, and achieves better performance with significantly less hardware resources requirement when compared to other conventional ring oscillator (RO), configurable RO (CRO), and reconfigurable RO (RRO) PUF designs. ERRO PUF requires only 6.25% of hardware resources to generate 1-bit PUF response when compared to other state-of-the-art CRO and RRO PUFs. ERRO PUF’s results show that the proposed model is suitable for enhancing a lightweight hardware security system and eliminating the need for trading security with area and power reduction.

Physical Unclonable Function (PUF) has been advocated as a promising solution for the hardware security of the Internet of Things (IoT). Nevertheless, the development of the IoT constrained devices is limited due to an important factor which is power. By leveraging the reversible logic paradigm, PUF can mitigate the power limitation. Integrating reversible logic into PUF alleviates the security and power challenges that limit the advancement in IoT and hardware security. To the best of our knowledge, this work is the first to design a cost-efficient reversible-based reconfigurable ring oscillator PUF (denoted as R3OPUF) for IoT and hardware security. The proposed design leverages the reversible logic paradigm and achieves better performance with significantly less hardware resources requirement compared to other conventional ring oscillator (RO)PUF, configurable RO (CRO), and reconfigurable (RRO) PUF designs. Quantum and comparative analysis for the R3O PUF is discussed in this paper. The proposed R3O PUF is able to generate more Challenge Response Pairs (CRPs) compared with state-of the-art RO PUFs with using an equal number of configurable logic blocks (CLBs) of an FPGA. R3O PUF requires only 50% and 25% of hardware resources to generate 1-bit PUF response compared to other CRO PUFs and RRO PUFs, respectively. R3O PUF’s results show that the proposed model is suitable for enhancing a lightweight hardware security system especially for root of trust (RoT), authentication and key generation applications and eliminating the need for trading the security with power reduction.

Bidirectional Encoder Representations from Transformers (BERT) based language models are a new class of deep neural networks with an attention mechanism. They emerge as a better alternative to the traditional recurrent neural networks for better sequence representation. They have achieved state-of-the-art performance in various natural language processing (NLP) tasks. Nevertheless, they demand intensive computation, energy, and memory requirements which pose a major challenge for their deployment on resource-constrained platforms and edge devices. To mitigate these limitations, this paper proposes a novel hardware accelerator design dedicated for BERT-based architectures with a reconfigurable functionality that improves circuit reusability and reduces hardware resources utilization. To the best of our knowledge, it is the first to present a holistic design and implementation of a reconfigurable hardware accelerator for BERT-based deep neural network language models. The proposed design leverages Fast Fourier Transform-based multiplication on block-circulant matrices for accelerating BERT weights matrices' multiplication. It is evaluated for different BERT-based model configurations on mainstream popular benchmarks while achieving a state-of-the-art performance. It is also evaluated for distinct batch sizes to study the impact of the batch size on the energy efficiency. A cross-platform comparative analysis shows that the proposed hardware accelerator achieves $6 \times, 27 \times, 3.18 \times$, and $8 \times$ improvement compared to $C P U$, and up to $1.17 \times, 1.77 \times$, $5 \times$, and $86 \times$ improvement compared to GPU in latency, throughput, power consumption, and energy efficiency, respectively. This design is suitable for efficient NLP on resource-constrained platforms where low latency and high throughput are critical.

With CMOS scaling moving toward an end, some “out-of-the-box” non-volatile memory (NVM) technologies come to life and promise to break the “memory wall”, fill the gap between memory and processor computation, and to cope with the limitations of conventional memory technologies that become limited in fulfilling the new requirements of the changing market trends. With the emergence of distinct NVM technologies, such as STT-RAM, PCM, and ReRAM, the concept of “universal memory” seems to be now achievable and about to have a far-reaching impact on the computing market. This paper studies each of the distinctive emerging non-volatile memories (STT-RAM, PCM, ReRAM) and presents their benefits, current limitations and trends, as well as their potential novel applications in a broad range of fields.

Nowadays, IoT has crossed all borders and become ubiquitous in everyday life. This emerging technology has a huge success in closing the gap between the digital and the real world. However, security and privacy become huge concerns especially in the medical field which prevent the healthcare industry from adopting it despite its benefits and potentials. This paper focuses on identifying potential security threats to the IoMT and presents the security mechanisms to remove any possible impediment from immune information security of IoMT. A summarized framework of the layered-security model is proposed followed by a specific assessment review of each layer.