Elisabetta Moisello

dblp:244/7595 · DBLP profile ↗
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13ranked-venue papers
4as first author
12since 2021 · last 2026
0000-0001-8535-4227ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 13 · 4 first-author · 12 since 2021
YearPublicationVenuePosition
2026 Voltage-Controlled Delay Line for Precise Phase Tuning of a 10-MHz Clock in Integrated Dual Active Bridge Converters
Francesco Romano, Elisabetta Moisello, Alessandro Liotta, Pietro Giannelli, Giovanni Frattini, Edoardo Bonizzoni, Piero Malcovati
ISCAS2
2026 A Comparative Study of Multilevel PWM Techniques with Circuit Non-Idealities in Class-D Audio Power Amplifiers
Chiara Rossini, Antonio Aprile, Elisabetta Moisello, Giuseppe Falcone, Francesco Rezzi, Edoardo Bonizzoni, Piero Malcovati
ISCAS3
2026 A 2.3-ns Response Time Temperature Insensitive Capacitive Level-Shifter with a Novel Active Pull-up for a 100-V Monolithic GaN Half Bridge
Tommaso Francesco Tardani, Andrea Gambero, Stefano Corona, Sandro Rossi, Antonio Aprile, Elisabetta Moisello, Giulio Ricotti, Edoardo Bonizzoni, Piero Malcovati
ISCAS6
2026 A 50-ns Response Time High-Side Current Sense with a Novel Analog Level-Shifting Technique for a 100-V Monolithic 1-μm GaN-on-Si Half Bridge
Tommaso Francesco Tardani, Andrea Gambero, Sandro Rossi, Antonio Aprile, Elisabetta Moisello, Giulio Ricotti, Edoardo Bonizzoni, Piero Malcovati
ISCAS5
2026 A 5.3-W 83.7% Peak Efficiency Simultaneous Wireless Power and Data Transfer IC Enabling 10-9 BER 540-kb/s Data Rate or Output Voltage Regulation
abstract
This paper proposes the first simultaneous wireless power and data transfer (SWPDT) integrated circuit (IC) which exploits a Capacitive-Inductive Channel (CI-Channel), enabling concurrent power and data transmission. The communication across the CI-Channel can support data-only transmission or can be incorporated into the system control loop, allowing output voltage regulation through phase-shift control applied at the primary side. The proposed IC can be configured as primary side (power transmitter, P-TX, and data receiver, RX) or secondary side (power receiver, P-RX, and data transmitter, TX). In order to ensure communication robustness, unwanted disturbances are removed through specifically designed Power Blanking and Ringing Blanking circuits. The proposed SWPDT IC test-chip prototype was fabricated using a 130-nm BCD process and experimentally verified considering the complete wireless power transfer (WPT) system, including primary side, CI-Channel and secondary side. The overall system, targeting medium-power industrial applications, achieves a maximum 5.3-W output power, a peak efficiency of 83.7% and a load regulation of 0.09 mV/mA. Moreover, a 540 kb/s data rate with no transmission errors across$10^{9}$bit acquisitions, corresponding to a bit-error-rate (BER)$\lt 10^{-9}$, was achieved.
Alessandro Liotta, Elisabetta Moisello, Giovanni Frattini, Pietro Giannelli, Piero Malcovati, Edoardo Bonizzoni
IEEE Trans. Circuits Syst. I Regul. Pap.2
2025 Control Loop Architectures for High-Frequency Switching-Mode DC-DC Buck Converters
abstract
This paper tackles the issue of control loops in high-frequency switching-mode DC-DC buck converters for post-regulation in automotive applications. Two different control loop implementations, designed in a 120-nm BCD process, are proposed and verified through simulations. Both solutions exploit the advantages of standard voltage mode control (VMC), while improving the transient response by including a one cycle (OC) and a feed forward (FF) loop, respectively. The OC VMC loop achieves 0.92 mV/V line regulation and 0.6 mV/A load regulation, whereas the FF VMC attains 0.17 mV/V line regulation and 4.8 mV/A load regulation, thus both outperforming the state-of-the-art of high-frequency switching-mode buck converters.
Filippo Boera, Elisabetta Moisello, Cristian Garbossa, Edoardo Bonizzoni
ISCAS2
2025 A Class-AB Slew Rate-Enhanced OTA for Triboelectric Sensing Interfaces in Smart Textiles
abstract
This paper proposes a three-stage operational transconductance amplifier (OTA) with slew-rate enhancing, especially designed for interfacing triboelectric nanogenerator sensors in smart textile applications. The proposed OTA, designed in a 130-nm BCD process, features 0.015-mm2area and 2.7-µW power consumption with 1.3-V supply voltage, while meeting the specifications of the targeted application, thus constituting a very compact low-power low-voltage solution. The proposed OTA was extensively simulated with Cadence Virtuoso, verifying its post-layout performance and robustness against process, voltage and temperature (PVT) variations.
Alessandro Fortunati, Elisabetta Moisello, Emmanuele Mozzorecchia, Emanuele Quartieri, Antonio Aprile, Edoardo Bonizzoni, Piero Malcovati
ISCAS2
2025 Controlled Single-Phase-Shift Modulation Method for a Fully Integrated Dual Active Bridge Converter
abstract
This paper focuses on control techniques for an integrated Dual Active Bridge (DAB) converter designed for low-voltage (5V) and low-power (2W) applications. The analysis concentrates on the single-phase-shift (SPS) modulation, as it offers the best balance between implementation simplicity and power efficiency for a control loop circuit that must be embedded within the system. Moreover, an innovative modulation technique called controlled single-phase-shift (CSPS) is introduced, which dynamically adjusts the phase-shift to maximize current flow through the load. This approach enhances the output power range by 33%, achieving an increase in the average efficiency throughout the phase-shift interval up to 4% when compared to the conventional SPS modulation. Circuit-level simulations have been conducted in Cadence Virtuoso environment to verify the effectiveness of the proposed approach.
Francesco Romano, Elisabetta Moisello, Alessandro Liotta, Pietro Giannelli, Giovanni Frattini, Edoardo Bonizzoni, Piero Malcovati
ISCAS2
2023 A Novel Capacitive-Inductive Channel for Wireless Power and Data Transmission
abstract
This paper presents a novel capacitive-inductive structure implementing the channel for power and data transmission in a wireless power transfer system. The structure consists of two$24-\mu\mathrm{H}$coil inductors, each surrounded with an open ring copper layer realized on a printed circuit board (PCB). The proposed channel structure allows simultaneous transmission of power and data: indeed power is transferred through the magnetic field generated by the coils, while data are modulated and transferred through the electric field produced by the capacitance determined by the copper rings and the parasitic capacitance of the two coils. The proposed structure was extensively studied and characterized both through simulations and measurements: compared to the state-of-the-art, in which metal plates placed below the coils are employed for implementing the capacitance used for data transmission, it shows a significant decrease in parasitic capacitance between the copper ring and the coil, thus reducing power disturbances on the data transmission.
Alessandro Liotta, Elisabetta Moisello, Giovanni Frattini, Pietro Giannelli, Piero Malcovati, Edoardo Bonizzoni
ISCAS2
2023 A 0.756-ppm/°C Time-Domain-Based Curvature-Compensated Bandgap Reference
abstract
This paper proposes a time-domain-based architecture for implementing a bandgap reference: indeed, the proportional-to-absolute-temperature (PTAT) voltage is provided by subtracting the gate-to-source voltages ($V_{GS}$) generated in two subsequent phases by the same diode-connected NMOS device, operating in subthreshold region and biased at different currents. As the same transistor is employed in both phases for the PTAT voltage generation, mismatch effects are inherently reduced. The proposed bandgap reference combines the PTAT and the complementary-to-absolute-temperature (CTAT) voltages by means of a switched capacitor difference amplifier and, if required, includes a dedicated sampling and filtering circuit. It features 5-bits trimming and implements curvature compensation through the addition of an integrated resistor with appropriate temperature dependence to the CTAT branch. The proposed bandgap reference circuit was designed in a standard 130-nm CMOS process and was extensively simulated in Cadence Virtuoso, achieving a worst-case 0.756-ppm/°C temperature coefficient.
Elisabetta Moisello, Edoardo Bonizzoni, Piero Malcovati
ISCAS1
2022 A Novel CMOS-SOI High-Responsivity Thermopile for Thermal Sensing Applications
abstract
This paper presents a novel micromachined high-responsivity thermopile sensor, fully compatible with standard CMOS-SOI (Silicon-On-Insulator) processes. The proposed thermopile features a versatile mosaic structure, based on 128 60 μ m × 60 μ m pixels connected in series and/or in parallel. Two versions of the proposed thermopile sensor, featuring a different number of equivalent pixels, are presented and fully characterized. The most performing of the two features $2.9\cdot 10^{4}\frac{V}{W}$-responsivity, outperforming other state-of-the-art thermopile sensors. The application of the most performing thermopile as proximity and motion detector was also verified through measurements.
Elisabetta Moisello, Michele G. G. Vaiana, Maria Eloisa Castagna, Antonella La Malfa, Giuseppe Bruno, Edoardo Bonizzoni, Piero Malcovati
ISCAS1
2022 A MEMS-CMOS Microsystem for Contact-Less Temperature Measurements
abstract
This paper presents a microsystem suitable for contact-less human body temperature measurements, as well as for presence, motion and proximity detection. It consists of a 130-nm CMOS-SOI MEMS (Micro-Electro Mechanical System) thermal sensor, referred to as “TMOS”, and its 130-nm CMOS interface circuit. The TMOS, based on a micromachined transistor, being an active device, features advantages in terms of internal gain: with optimal biasing, indeed, the TMOS achieves 274-$\mu \text{V}/^\circ \text{C}$input-referred sensitivity at 3-cm distance and 50.33° field-of-view (FOV), outperforming thermopile detectors. The sensor and the interface circuit, featuring a chopper-stabilized-based analog readout with a 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter), were mounted in the same package and extensively measured: the microsystem achieves repeatability and ±0.17°C precision, thus satisfying the requirements for contact-less human body temperature measurements; furthermore, its performance as presence, motion and proximity detector was also verified.
Elisabetta Moisello, Michele G. G. Vaiana, Maria Eloisa Castagna, Giuseppe Bruno, Igor Brouk, Yael Nemirovsky, Piero Malcovati, Edoardo Bonizzoni
IEEE Trans. Circuits Syst. I Regul. Pap.1
2019 A Chopper Interface Circuit for Thermopile-Based Thermal Sensors
abstract
This paper presents a readout circuit for thermopile-based thermal sensors, suitable for contactless temperature measurements. The circuit, designed and extensively simulated in a standard 130-nm CMOS process, employs chopper stabilization in order to minimize offset and noise contributions at low frequency, while providing proper amplification to the input signal, which behaves substantially as a DC. The circuit nominal supply voltage is 1.2 V and its power consumption is approximately 260 μW. The proposed single-ended architecture solves the drawbacks of the most straightforward fully differential approach, while achieving a simulated input-referred residual offset mean value equal to 84.4 nV, with 487 nV of standard deviation. An accuracy of ±0.3°C is provided at room temperature, making the circuit suitable for medical devices, such as contactless fever thermometers, and security systems, such as motion and human presence detection sensors.
Elisabetta Moisello, Michele G. G. Vaiana, Maria Eloisa Castagna, Giuseppe Bruno, Edoardo Bonizzoni, Piero Malcovati
ISCAS1