Active RC-Integrators are one of the main building blocks of continuous-time Delta-Sigma-Modulators (CTDSMs). The DC gain and gain-bandwidth product (GBW) of their Operational Ampifiers (OAs) play an important role in the modulator stability and performance in terms of signal-to-quantization-noise ratio (SQNR) as well as spurious-free dynamic range (SFDR). Negative-R assisted integrators have been introduced to reduce the CTDSMs sensitivity to OA non-idealities, where the negative-R has shown linearity improvements in low-power CTDSMs for relatively narrow bandwidth applications. However, the negative-R concept has not been widely applied for wideband applications. Wide-band CTDSMs in particular are more sensitive to the non-idealities of the OA GBW and especially in the associated phase-shift compared to their narrow-band counterparts. This paper provides insight into the effect of negative-R assistance on the GBW of the OA, where it is shown, that the phase-shift of the integrator due to finite GBW is not reduced by the negative-R assistance, and still remains an issue to be considered in the design of a wide-band CTDSMs.

This work presents a 600MS/s 10-bit single-channel asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) using a highly linear unit via-based delta-length capacitive digital-to-analog converter (C-DAC). The plain and regular segmented C-DAC structure is presented in detail, which provides close to 13-bit static matching with an area of only 1160 μm2. A Flash ADC is employed to pre-load some MSBs for improved conversion speed while also efficiently utilizing DAC segmentation, which is practically necessary in delta-length-based C-DACs. This ADC architecture can easily be extended to a time-interleaved SAR to fully take advantage of the fast Flash conversion. The ADC was fabricated in a 22nm FDSOI technology and achieves a SNDR of 51.37dB at 600MS/s with near Nyquist input while consuming 3.04mW from a 0.85V supply, which leads to a Walden FoM of 16.74fJ/conversion-step.

As wideband Delta-Sigma-Modulators (DSMs) are restricted in oversampling ratio (OSR), and low OSR reduces the benefit of higher order loop filters, the increase of the internal resolution is an obvious way to achieve high signal-to-quantization-noise ratio (SQNR). State-of-the-art implementations restrict the internal resolution to mostly 4-6 bits, as efficient QTZs with higher resolution add excessive delay into the DSM. Multi-step or time-interleaved-quantizer (TI-QTZs) are an effective way to enhance resolution at high sampling rate, but the resulting latency in excess of one clock cycle usually prohibits their usage in DSMs. This paper proposes a new architecture to employ high resolution multi-step QTZs, such as TI SAR or pipeline ADCs. In the proposed architecture, an excess loop delay (ELD) of several clock cycles in the LSBs is purposefully allowed. While the MSBs are conventionally ELD-compensated, the LSBs are not. The resulting error is corrected in the digital domain. It is shown that matching requirements are relaxed by first-order shaping. The idea is also applicable to a Leslie-Singh and noise-coupling architecture, which are compared to the proposed architecture in an extensive system-level analysis and simulation. Depending on the target application, an advantageous design recommendation can be given based on the presented results depending on OSR, internal bitwidth and expected analog-digital matching.

Excess loop delay (ELD) in high speed continuoustime (CT) Delta-Sigma-Modulators (DSMs) imposes design challenges and limits the use of high resolution, e.g. successiveapproximation-register (SAR) based internal quantizers, as usual compensation techniques like the use of a direct path around the quantizer come with increased swings and reduced maximum stable amplitude (MSA). In this paper, two bitwise ELD compensation approaches applicable to cascade-of-integrators with distributed feedback (CIFB) loop filters are proposed, which alleviate this problem for SAR and other multi-step quantizers by sequentially feeding bits into the feedback loop when they are available (MSB first, LSB last). Loop-filter equivalence for such bitwise ELD compensation is analytically derived. System-level simulations using Matlab & Simulink for exemplary 4-bit 2nd, 3rd and 4th-order modulators show 40% reduction of the last integrator output swing compared to the conventional direct path compensation. This potentially allows to avoid the swing, quantizer scaling and noise trade-offs due to ELD in state of the art designs.

The performance of a 0-X MASH DSM is primarily defined by the DSM noise-shaping and the inter-stage gain (ISG). Due to system specification like modulator order and OSR, the DSM noise shaping is limited. All further performance in the 0-X MASH modulator is achieved by setting a large ISG, which amplifies the residue signal before it is processed by the fine stage DSM. This paper presents an analysis of the factors influencing the ISG and proposes measures, which can be used to maximize it. Most importantly, it is shown, that the CIFB DSM architecture is preferred, since the wideband residue overloads the CIFF architecture with its peaking OOB STF much earlier, thus CIFB results in more ISG and less internal swings. The presented analysis can be used as a guideline for achieving optimum performance in a 0-X MASH DSM and yielding the maximum SQNR.

Electrical Impedance Spectroscopy (EIS) is a popular method for investigating tissue properties. Implementing the signal generator for EIS measurements with a suitable excitation signal type is thereby one of the two system components. The choice of the excitation signal defines the measurement speed, signal-to-noise ratio (SNR), total area and power consumption of the system, and many more properties. Signal types such as analog single-tone, analog multi-tone, linear feedback shift registers (LFSR), and single-tone Sigma Delta Modulated (ΣΔM) are proposed in the state of the art. In this work an EIS setup is implemented and successfully tested with all the mentioned signal types to evaluate their properties on impedance models as well as in vitro cell layers. It is proposed to combine the ΣΔM with the multi-tone excitation signal yielding a very versatile excitation generator. Multi-tone ΣΔM are as fast as analog multi-tones, while benefiting from a binary output and thus less system complexity. The implemented EIS setup is used to perform EIS measurement for biological samples. The results show a very good matching with the reference for all the excitation signals.