This paper presents a 1stOrder Quasi-Passive Sigma-Delta Modulator developed in 65 nm technology which fits in a 30 × 36 µm2area, for applications in Organ-on-Chip systems. In these systems, low power dissipation is crucial to avoid heating biological parts and to maintain a stable temperature. It is also desirable to have ultra-compact analog-to-digital converters so the signals from a single cell or a single sensor of a large sensor matrix can be individually conditioned. This circuit fills a gap in low to medium-frequency efficient compact analog-to-digital converter literature. The circuit achieves an area smaller than 1080 µm2and power consumption lower than 10 µW while having an SNDR of 51.1 dB, and thus, an ENOB of 8.2 bit, as well as a bandwidth of over 50 kHz.

This paper describes a course offered in the Master program in Electrical and Computer Engineering of Instituto Superior Tecnico, Universidade de Lisboa, and offered within the GreenChips-EDU platform. The course is on Ultra Low Power Circuits design. The novelty of this course is that the emphasis is on design of analog and digital circuits with CMOS technology using the transistors in subthreshold region, and less conventional low power topologies for RF circuits. The course uses professional CAD tools, currently "Cadence Design Framework II", and on production materials for the use of "Synopsys Custom Compiler", configured with a foundry technology design kit with precise modelling in all regions of operation of a MOS transistor. The design flow procedure is in accordance with common practices used in the industry. The proposed model has been classroom tested in the last three years with positive student reviews on course quality assessment.

Ring oscillators are widely used in modern applications due to their simplicity, compact size, and low power consumption. Their oscillation frequency is determined by the number of stages (or inverters) and the average delay per inverter. In advanced submicron technologies, logic gates’ minimal propagation delay allows high-frequency operation with great efficiency. However, ring oscillators become increasingly power-inefficient at lower frequencies (MHz range). This paper presents a novel oscillator topology that combines two injection locked stacked ring oscillators with different stage counts, generating two output frequencies with a fractional ratio. The stacking technique reuses the supply current while splitting the available supply voltage across the two oscillators. This approach effectively reduces the oscillation frequency while maintaining energy efficiency and improving phase noise performance by approximately 3 dBc/Hz across all frequencies. Simulation results in TSMC 65nm confirm that the locking mechanism of two stacked ring oscillators is achieved, even when they contain different numbers of inverters, enabling fractional injection locking.

Advances in bioelectronic medicine have led to a reduction in implant size and notable improvements in energy management and data transmission techniques. Bulky titanium casings traditionally used to shield implant electronics are being gradually replaced by more streamlined materials, primarily composed of polymers and thin film ceramics. This transition offers numerous advantages, including a smaller form factor, enhanced flexibility, and the facilitation of wireless power and data transmission. However, it is essential to acknowledge potential drawbacks of these innovative encapsulation materials, such as the unknown longevity and adhesion issues that may compromise hermeticity. To investigate the hermeticity and long-term performance of conformal encapsulations, we propose a fully encapsulated wireless monitoring system with novel circuitry. The system comprises energy harvesting, humidity assessment, and passive communication. In this paper, we delve into each of these areas, presenting innovative solutions that are later implemented and tested. The final system is realized in an integrated circuit technology of 65 nm, fitting in a compact area of 0.3 mm2 ($76~\%$occupied by the integrated receiver coil), while consuming$1.3~\mu $W. All the necessary components are fully integrated, allowing for increased miniaturization and lower power consumption.

This paper investigates the use of model-based reinforcement learning in the context of ad hoc teamwork. We introduce a novel approach, named TEAMSTER, where we propose learning both the environment's model and the model of the teammates' behavior separately. Compared to the state-of-the-art PLASTIC algorithms, our results in four different domains from the multi-agent systems literature show that TEAMSTER is more flexible than the PLASTIC-Model, by learning the environment's model instead of assuming a perfect hand-coded model, and more robust/efficient than PLASTIC-Policy, by being able to continuously adapt to newly encountered teams, without implicitly learning a new environment model from scratch.

A qualitative analysis using different optical water types (OWTs) can be easily and efficiently applied by entities outside scientific research in water quality monitoring programs, as well as in the creation of alert systems for rapid deterioration of water quality. In this study, we present the monitoring of different OWTs using the MERIS, OLCI, and MODIS instruments, onboard satellites, during the period 2003-2022 over the entire Alqueva reservoir and also for five distinct areas of the same reservoir. It was found that the northern area of the reservoir consistently presents the worst water quality, not only in terms of microalgae bloom intensity but also in turbidity of the water due to the characteristics of the reservoir in this area. The increasingly warm autumns in Portugal are leading to a more intense microalgae blooms occurring in the fall.

ESA's$9^{\text{th}}$Earth Explorer, the Far-infrared Outgoing Radiation Understanding and Monitoring (FORUM) mission aims to record the emission spectrum of the Earth's stratosphere and troposphere in the spectral range of 100$\text{cm}^{-} 1$to 1600$\text{cm}^{-1}$(between 6.25$\mu \mathrm{m}$and 100$\mu \mathrm{m}$). The payload is composed of the FORUM Sounding Instrument (FSI), a Fourier Transform Spectrometer (FTS) scanning the Earth atmosphere in a step-and-stare acquisition mode, sounding a 15 km diameter Field Of View (FOV) with a ground sampling distance of 100 km and providing a spectral resolution of 0.5$\text{cm}^{-1}$. Additionally, a thermal infrared imager called FORUM Embedded Imager (FEI) is co-located with the footprint of FSI providing a FOV of 36 km$\mathrm{x}\ 36$km, covering a spectral band centred at 10.5$\mu \mathrm{m}$with a bandwidth of 1.5$\mu \mathrm{m}$. This paper provides a summary of the mission objectives and requirements, and shows the system overview and architecture. Furthermore, we discuss key technology developments and finally the mission outlook is shortly described.

Cardiovascular diseases are one of the major causes of death worldwide, which drives the research on smart catheters for early diagnosis. Deploying ASICs at the tip of the catheter is challenging, as power is delivered through a long and thin wire, limiting the power integrity. Also, since the catheter needs to fit into the diameter of a blood vessel or other narrow channel in the human body, there is no room for bulky decoupling capacitors. Finally, power consumption must be optimized, as the energy density may lead to prohibitive heating of tissues and fluids. Still, while targeting better performance, e.g. higher imaging resolution, the requirements for bandwidth and accuracy consistently increase, ultimately demanding precise on-chip clock generation for communication and digitization. In this paper we propose a circuit for at-the-tip clock generation in smart catheters, comprising a low-drop out (LDO) regulator, voltage and current references and a low-jitter digitally controlled oscillator (DCO). The clock generator also comprises a clock divider with programmable duty cycle, allowing system reconfiguration. The circuit is laid out and simulated under application conditions. The LDO achieves a full-spectrum power supply ripple rejection (PSRR) of 50 dB with an output load of 10 mA. The DCO, supplied by the aforementioned LDO, achieves a phase noise of -104.5 dBc/Hz at an offset of 1 MHz and 1.25 GHz of oscillating frequency. The proposed clock generator allows digitization at 200 MSps with a maximum SNR of 56.3 dB for an input signal of 50 MHz if phase noise is integrated from 100 kHz to 625 MHz.

Ring oscillators are one of the simplest, smallest and most energy-efficient topologies when it comes to clock generation. Being implemented using a chain of digital inverters, their oscillation frequency can be set by the inverters count in the chain and the delay of each inverter. This is an advantage when considering the simplicity and size, however, it is also the cause for high frequency variation with temperature. In this paper we propose an ultra-low power oscillator circuit that exploits a stack of small ring oscillators for supply current reuse and injection locking, which provides phase noise improvement. Frequency stability is achieved through a feedback loop that relies on a frequency-to-voltage converter with improved linearity and reduced temperature sensitivity based on MOS capacitors. Simulation results show that the oscillation frequency changes ±0.4% from 0 to 70°C (57 ppm/°C) while consuming 2.4 μW at 10 MHz, with a phase noise of -88.9 dBc/Hz at 100 kHz offset.

The ring oscillator is the topology of choice in many modern applications given its simplicity, small area footprint, low-power and ability of being implemented with digital inverters. The oscillation frequency is dictated by the number of stages in the chain and the average delay of the inverters. In deep submicron processes, the very short propagation delay of logic gates makes the ring oscillator a very energy-efficient solution for high frequencies of operation, whereas for low frequencies the efficiency generally drops because larger capacitances must be driven to slow down the transitions. In this paper we propose a topology of oscillator that employs four injection-locked stacked ring oscillators, reusing current while the available supply potential is divided among these stages, naturally reducing the oscillation frequency while maintaining energy efficiency. The output signal is recovered to the supply rails through a level shifter circuit with feedback, allowing to adjust its threshold to deal with PVT variations. Simulation results show that the circuit operates from 3-10 MHz, while consuming 0.7 μW at 10 MHz, with a phase noise of -88.8 dBc/Hz at 100 kHz offset, leading to a FoM of -160 dB.

In recent times, infrastructure-free indoor positioning has been an important topic of research. Many of the proposed systems are based on pedestrian dead reckoning, thus relying on estimating the heading of the pedestrian. While many studies successfully address the problem of estimating the heading of the device, current approaches have the limitation of requiring the device to be aligned with the pedestrian. To address this problem, we propose an algorithm for estimating the misalignment between the pedestrian and the device by evaluating the acceleration data fit a simplified gait model in each direction. Contrary to similar algorithms, the proposal in this paper does not require a previously trained model nor the detection of steps, and can be implemented using only acceleration data. Furthermore, our experimental results show a significant improvement over the current state of the art.

Discrete-time ΣΔ generally rely on switched-capacitor implementations that require operational amplifiers to implement the integrators. For ultra-deep submicron processes, the limited intrinsic gain of the transistor hinders the design of operational amplifiers. This paper proposes a topology for ΣΔ modulators that employs a low-power quasi-passive integrator. The input voltage is converted into the chargedomain by a transconductor-based front-end. The integration process is implemented with MOS capacitors instead of linear capacitors, which allows the reduction of charge leakage. While this design targets relatively low resolutions, due to the nonlinear nature of the passive integration, the absence of operational amplifiers enables the topology to fit in a very small area. The topology is validated by simulations with the design of a 1storder ΣΔ modulator. The circuit is designed in a 0.13 μm technology, fits in 40 × 60 μm2, performs at 100 MSps with 51.34 dB of SNDR and consumes 0.08 mW.