This work presents a chemical readout system designed in TSMC 180 nm technology. The proposed design has an input range of 0-1.8 V, linearity (R2) of over 0.997, high sensitivity of 600 KHz/pH, a maximum frame rate of 1.4 μ$s$and a small chip area. The readout system includes an Ion-Sensitive Field Effect Transistor (ISFET) front-end that works in the saturation region, trans-linear circuits for linearity enhancement, and a CCO (Current Controlled Oscillator)-based ADC as an analogue to digital converter. This system was designed to provide a good balance between input range, linearity, and silicon area. The proposed architecture is capable of compensating for 400 mV of trapped charge by changing the biasing current of the lineariser as a universal quadratic equation solver.

This paper presents a winner-take-all (WTA) approach for implementing background inhibition in neuromorphic Ion-Sensitive Field-Effect Transistor (ISFET) arrays. The integration of WTA, integrate and fire (I&F) and CMOS-based electrochemical readout paves the way for the next generation of Lab-on-chip (LoC) platforms to diagnose and classify infectious diseases using sensor learning. The integration of the WTA in individual pixels allows for spatial adaptive filtering which can help eliminate the dynamic background due to ion accumulation at the gate of the sensors. The readout is done through address-event representation (AER) to enable ultra-low power data acquisition. The cluster implementation makes the design scalable for implementation as part of a large-scale integrated sensor. The paper proposes a novel ultra-low powered approach where the pixel power consumption ranges from 171.6nW to 410.9nW with an expected sensitivity of 20.2 KHz/dpH to 29.1 KHz/dpH. The sensor array is implemented in TSMC 0.18$\mu\mathrm{m}$.

This paper introduces a linear weighted integrate-and-fire (I&F) neuron architecture for Ion-Sensitive Field-Effect Transistors (ISFETs). It contributes to the next generation of neuromorphic lab-on-chip (LoC) platforms with the aim to integrate electrochemical sensors with neural networks on-silicon to compensate for sensor non-idealities. The neuron consists of a readout circuit, a linear voltage-controlled weighting circuit, and a robust I&F circuit with low power consumption. Notably, the readout in the neuron circuit achieves linear conversion of input voltage to output current at low power. This work also presents a cluster architecture for spatial correlation of trapped charge effects and process variations. The calibration system integrated in each cluster is realized using a current bit cell chain inspired from the current mode algorithmic ADC. The compensation range for each pixel ranges from −157.7 mV to 128.1 mV. The system is implemented as a $25\times 20$ cluster array, and the sensitivity of each cluster is 10.92 kHz/pH.

We present the next step of neuromorphic ISFET arrays with spike domain encoding and spatial device compensation. Each pixel provides a spiking signal with a frequency related to the pH in solution and expected sensitivity of 48.6 to 112.2 kHz/dpH. The array is arranged as clusters which use regulation to cancel undesirable sensor offset and then linear interpolation for temporal drift during the readout. The scheme relies on spatial correlation of ISFET behaviour which is demonstrated with a low standard deviation of 11.6 mV sensor offset, which is well in the pixel compensation range of ± 500 mV. On an array level, address-event representation is used for external signal handling, which enables low power and scalable throughput. The array chip is implemented in TSMC 0.18 μm CMOS technology.