In this paper, we propose a triple-mode baseband (BB) receiver (RX) architecture for cyclic prefix orthogonal frequency division multiplexing (CP-OFDM) with weighted overlap and add (WOLA) technique. The system specifications follow the IEEE 802.11ad/ay standard for next-generation millimeter wave communications. This BBRX is a flexible and expandable architecture due to the modularized, parameterized, and feed-forward data flow design strategies. The non-ideal circuit effects, such as frequency offset, phase noise, power amplifier (PA) non-linearity, and adjacent channel interference are jointly considered for the overall performance evaluation. The simulation results show that CP-OFDM with WOLA (W-CP-OFDM) and filter bank multicarrier (FBMC) present similar out-of-band performance while considering PA non-linearity. The synthesis results indicate that the W-CP-OFDM/FBMC has 2.1%/97% gate count increased overhead as compared to CP-OFDM.

Channel estimation is a crucial issue for hybrid multiple-input multiple-output architecture of wideband wireless millimeter wave system. In this paper, we present a hardware implementation of channel estimation based on compressive sensing method. We exploit sparsity in channel space and take advantage of both the time domain and the frequency domain to effectively reduce the computational complexity. We then disassemble the sensing matrix into smaller dimensional matrices to further simply the sensing formula by utilizing the orthogonality of the DFT codebook. The sensing issue is solved by the generalized orthogonal matching pursuit with Cholesky decomposition techniques, which achieves a significant reduction in the number of computations. Finally, we evaluate the performance of the proposed method with the perfect channel state information, and hardware performance by fixed-point analysis and RTL design and synthesis results.

This article proposes a digital two-stage phase noise (PN) compensation and residual carrier frequency offset (rCFO) and residual sampling clock offset (rSCO) tracking module in the baseband receiver side for single carrier (SC) systems in the millimeter-wave (mmW) band. The proposed two-stage PN compensation and rCFO/rSCO tracking module (2STG-PNC&T) includes a correlation-based linear interpolation method for the common phase error (CPE) of the low-frequency PN, a subsymbol CPE compensation with a reformed low-complexity π/4robust PN slicer for the high-frequency PN, and a tracking mechanism for rCFO and rSCO estimation on 64-QAM under the harsh PN condition of the frequency synthesizers used in the mmW band. The proposed module can restrict the maximum rCFO/rSCO within ±0.4 ppm and track the phase error caused by the PN successfully. Besides, the compensated power spectral density of the residual PN is reduced from -90 to -125 dBc/Hz at 1-MHz offset. A four-time parallelism architecture of the new 2STG-PNC&T is proposed to work at a 625-MHz clock rate under 64-QAM for 15 Gb/s transmission. The gate count/power of the proposed design is only 4.0%/6.9% of the overall digital baseband, respectively.

This article presents a high-throughput and low-routing complexity low-density parity check (LDPC) decoder design based on a novel second minimum approximation min-sum (SAMS) algorithm. The routing congestion is mitigated by reducing the required interconnections in the critical path of the routing network. The implementation and postlayout results with 28-nm 1P9M CMOS process show that the proposed design can achieve a throughput of 10.5 Gb/s for a millimeter-wave 60-GHz baseband system while satisfying the low bit error rate (BER) requirements (10-7). The proposed design reduces the wiring in the routing network by 21% and improves the area by 12% compared to the conventional min-sum (MS) and normalized MS (NMS) algorithm. Additional hardware optimizations are obtained by considering the internal message passing resolution based on the BER and signal-to-noise ratio (SNR) requirements for a practical baseband system. The power consumption is efficiently reduced by the employment of a shared address generator that exploits the degree of parallelism to reduce the switching activity on a group of memory elements. The LDPC decoder is implemented with a core area of 0.14 mm2, power consumption of 81 mW at 312.5 MHz, and the area and power efficiency of 75 Gb/s/mm2and 10.2 pJ/bit, respectively.

A 50Gb/s all-digital adaptive noise-suppression (NS) feed-forward equalizer (AFFE) and adaptive decision feedback equalizer (ADFE) for 2-level pulse amplitude modulation (2-PAM) serial link systems is presented. Based on a parallel extended incremental coefficients-lookahead scheme (EICL), we propose a Dual Data-paths Self-Lookahead Filter (DD-SLF) for ADFE. DD-SLF architecture has better energy efficiency and hardware area than an original SLF architecture due to the number of delay elements in the feedback loop is reduced. Furthermore, gated clock technique with the design idea of register file architecture is used to replace the pipelined delay elements to save power. The whole equalizer which operates at 1GHz system clock rate with 50 parallelisms is implemented in 40nm CMOS technology with a 0.38mm2core area. The equalizer with 50Gb/s throughput rate achieves 2.6pJ/bit energy efficiency under 0.81V supply measurement results.