This paper provides insights on three different possibilities, for transferring data gathered by one field-programmable gate array (FPGA) design to a second one. Typical use case are scenarios where some initial calibration needs to be performed, before a special controller algorithm can be applied. For demonstration and evaluation purposes, this paper uses a real world, active noise control (ANC) application as an example scenario. This application requires specific memory elements of various types to be static while as much of the remaining hardware resources as possible shall be changed dynamically between two configurations. The first approach uses a serial communication protocol to extract the data from the first configuration and insert it into the second configuration. The second approach uses the classic dynamic partial reconfiguration (DPR) design flow for Xilinx FPGAs. The third approach, which is a novel approach, uses a technique called context save restore (CSR) that is not officially supported by the vendor. This technique manipulates the second configuration bit file to import the data, previously gathered by and extracted from the first configuration bit file. Not by means of an additional communication interface, but by exploiting the features of an FPGAs configuration interfaces. The advantages and disadvantages in terms of hardware resource overhead, processing demand and feasibility of these three approaches are evaluated and discussed.

The most used algorithm in active noise control (ANC) applications is the filtered-x least mean square (FxLMS). For large scale systems with multiple inputs and outputs the computational demand of the FxLMS is rising rapidly. Conventional solutions, running on digital signal processors (DSPs), have limitations in parallel computing. In this work a parameterizable multiple input-multiple output (MIMO) feedback FxLMS architecture for field-programmable gate array (FPGA) platforms is presented that can easily be optimized for high-performance or resource efficient computation. The implementation is validated in a real-time practical application using an active headrest with 2x2 channels. The noise reduction is evaluated over various configurations with increasing performance and the respective synthesis results are presented. Here the noise reduction does benefit from the additional computational performance gains. An additional configuration with llxll channels and filter lengths of 2049 at a sample rate of 40 kHz is shown as a benchmark on high-end FPGAs.

In this paper a field programmable gate array (FPGA) is considered as a digital signal processing platform for the implementation of an exponential sine sweep measurement algorithm. Aiming at minimizing the required computational resources, two strategies are proposed. Firstly, an oscillator implemented with the coordinate rotation digital computer (CORDIC) algorithm is used to generate the exponential sine sweep. Secondly, only the calculations are performed that lead to the linear impulse response of the system for a desired length. Furthermore, aiming at minimizing the required memory resources, the measured impulse response is stored in the memory previously allocated to the recorded signal. In order to validate the proposed implementation, measurements of an acoustical system are performed using a platform that is equipped with an FPGA and a processor. In this way, the results achieved by the FPGA fixed-point implementation can be compared to reference results achieved using a floating-point MATLAB implementation running on the processor. This comparison corroborates the validity of the proposed implementation.