In advanced technology nodes, the impact of the back-end-of-line (BEOL) on chip performance and power consumption becomes progressively significant. This paper presents a BEOL configuration pathfinding framework using the proposed cross-technology transferable reinforcement learning (CTRL) model. We optimize the BEOL technology parameters, including the metal stack, geometry, and design rules, to enhance the power efficiency and performance resulting from the physical design process. First, we extract various design and technology features and embed them into metal-type-wise deep neural networks. Our multi-policy model selects a BEOL parameter configuration that is estimated to improve chip power efficiency and performance. We employ a policy gradient algorithm complemented by various training strategies, such as data normalization, action-reward buffer, and network optimization, to expedite training convergence. Furthermore, we transfer the pathfinding knowledge from the trained model in the old node to the new model for efficient BEOL configuration pathfinding in the advanced node, referred to as cross-technology transfer learning. The proposed framework achieved 19 % reduced total power consumption, 68 % improved worst negative slack, and 87 % improved total negative slack with a high reward efficiency, on average, in several designs. Further, we demonstrate that the reward efficiency of our proposed CTRL model outperforms that of the conventional fine-tuning method in transferring knowledge by 24 %.

We introduce RL-Fill, a novel reinforcement learning framework for timing-aware fill insertion. RL-Fill first generates a large number of fills in the empty spaces and then removes the timing-critical fills as determined by the policy network. Towards faster convergence and stability, our framework employs a two-phase training process. In the first phase, we train the policy with offline expert data using an imitation learning scheme. In the second phase, we further optimize the policy with online data using reinforcement learning. Moreover, we propose a new data augmentation method, LayoutMix, to ensure data-efficient training despite limited number of expert data. Our results demonstrate that RL-Fill is competitive to the commercial tool and outperforms the previous machine learning-based method in timing metrics while adhering density constraints.

Cell legalization order has a substantial effect on the quality of modern VLSI designs, which use mixed-height standard cells. In this paper, we propose a deep reinforcement learning framework to optimize cell priority in the legalization phase of various designs. We extract the selected features of movable cells and their surroundings, then embed them into cell-wise deep neural networks. We then determine cell priority and legalize them in order using a pixel-wise search algorithm. The proposed framework uses a policy gradient algorithm and several training techniques, including grid-cell subepisode, data normalization, reduced-dimensional state, and network optimization. We aim to resolve the suboptimality of existing sequential legalization algorithms with respect to displacement and wirelength. On average, our proposed framework achieved 34% lower legalization costs in various benchmarks compared to that of the state-of-the-art legalization algorithm.

Accurately predicting routing congestion caused by netlist topology is essential as circuit designs become increasingly complex. To correctly predict routing congestion, the use of graph neural networks (GNNs) has gained great attention. However, existing GNN-based methods have limitations in capturing crucial netlist information and effectively representing complex topologies. In this work, we propose a novel approach, ClusterNet, to predict routing congestion caused by netlist topology. Our approach leverages netlist clustering to overcome these limitations. We first divide the netlist into highly connected clusters using the Leiden algorithm, enabling an analysis of the local netlist topology. We then predict routing congestion by exploiting GNNs to generate cluster embeddings that capture the detailed netlist topology. In addition, we introduce a cluster padding method that utilizes the trained model to mitigate routing congestion. By applying the proposed ClusterNet, we can accurately predict and optimize routing congestion from specific cluster topologies. Our experimental results demonstrated improved prediction performance, with a mean absolute error of 0.056 and an R2 score of 0.669. Furthermore, routing congestion optimization significantly improved the total negative slack and reduced the number of failing endpoints by 14.5% and 9.9%, respectively.

Many design optimization methods using machine learning (ML) techniques have been investigated to reduce the number of design iterations in the physical design flow. The demand for big data to support ML research has been increasing, but the lack of place-and-route (P&R) benchmarks is one of the major problems. We propose a framework to construct realistic P&R benchmarks for use in training ML applications. The framework can organize the P&R database using an artificial netlist generator, which can create any gate-level netlist from user-specified input parameters that represent the topological characteristics of the circuit. We show that a training dataset that contains many artificial gate-level netlists can improve the generalizability of the model to predict the routability for unseen real circuits without using expensive real-world data. Compared to the model that had been trained with real-world circuits, we improved the F1 score in predicting the timing and routing failure by 26.4% and 54.5%, respectively.

We propose a fast interposer bus router that observes the complex design rules of silicon interposer layers and optimizes the signal integrity. By escaping highly integrated physical layers (PHYs) of chiplets and sharing the same bus topology, our router compactly interconnects thousands of bump I/Os within a short timeframe. In addition, we secure the maximum wire pitch and guard the signal wires to optimize the signal integrity in high bandwidth. Compared with the results of a commercial EDA tool, our router is about five times faster and the results are verified to transmit signal in a target data rate with 30% improved eye width and 35% improved eye height for industrial designs. Our router can provide practical routing results for the upcoming 2.5D ICs that have more chiplets and require higher bandwidth than the existing chips.

Recent routability research has exploited a machine learning (ML)-based modeling methodologies to consider various routability factors that are derived from placement solution. These factors are very related to the circuit characteristics (e.g., pin density, routing congestion, demand of routing resources, etc), and lack of circuit benchmarks in training can lead to poor predictability for ‘unseen’ circuit designs. In this paper, we propose a machine learning (ML) framework for early routability prediction modeling. The method includes a new artificial netlist generator (ANG) that generates an artificial gate-level netlist from the user-specified topology characteristics of synthetic circuit, even with real world circuit-like. In this framework, we exploit that ANG that supports obtaining ground truths for use in training ML-based model, the training dataset that have a wide range of topological characteristics provides strong ability to inference noisy, previous-unseen data. Compared to a design-specific training dataset [4] that is used for routability prediction modeling, we increase the test accuracy of binary classification (‘pass' or ‘fail’) on timing, DRC and routability by 6.3%, 8.6% and 6.6%, and reduce the generalization error [12] by as much as 87% compared to design-specific training dataset [4].

In bus routing, if signal bits in a bus structure share a common routing topology, routability is increased by avoiding twisted patterns and variation immunity. The bus routing problem has become significantly important because of increasing complexity of bus structures for multichip-module, I/O pins, or on-chip memories in advanced technology. We present and evaluate a compact topology-aware bus routing method that can both compactly synthesize the routing topology of the bus and minimize design rule violations even in designs with high bus density and high track utilization. Our proposed method completed the bus routing in the runtime limit of the ICCAD-2018 contest and achieved 66% reduction in total cost compared with the winner of that contest.

Variation-aware leakage analysis becomes an essential design process as the technology node continuously shrinks. This article proposes a novel additive statistical leakage analysis method that uses exponential mixture model (EMM) to estimate the leakage distribution. Using a few leakage data for sub-blocks of an input circuit, we estimate any shape of leakage distribution regardless of new process nodes or operating conditions. Leakage distribution of an input circuit can be obtained by adding the leakage distributions of the sub-blocks. The proposed addition step sequentially adds the leakage distributions of sub-blocks that are expressed as EMMs. Before the addition step, we improve the accuracy by handling linear dependence among leakage simulation data of sub-blocks. In addition, we propose a method to reduce the number of components of an EMM to prevent exponential increase in runtime and memory during the addition process. The proposed method achieved 43.6 times improvement in goodness-of-fit of the estimated cumulative density functions compared to the best results of other analytic model-based methods.