Screening for frequency-dependent failures that comprise a significant proportion of Silent Data Errors (SDE) in microprocessors is addressed using timing-aware scan tests. Silicon experiments targeting SDE-sensitive modules in the Core of a recent data center product is performed using such tests. Vmin measurements with these tests demonstrate the promise of this approach.

Finding tests for hard-to-detect (HTD) faults in complex designs is challenging. Researchers use testability measures to guide automatic test pattern generation (ATPG) programs to improve fault detection efficiency. However, each measure favors the detection of specific faults in the same circuit. Principal component analysis (PCA), an unsupervised learning technique, has been used to combine several algorithmic testability measures. Guidance from the PCA measure was found to uniformly improve the ATPG efficiency with fewer backtracks, lower ATPG CPU time, detection of many HTD faults, fewer aborted faults, and increased fault coverage. The present work shows that these benefits continue further when we also included topological factors like fan-in and fanout cone base widths, fanout reconvergence data, and even-odd inversions on reconverging paths in a new-PCA measure. This work opens the venue for ongoing improvements.

The exponential complexity of automatic test pattern generation (ATPG) necessitates the use of heuristics in making choices during test generation. However, in practice no single heuristic fits all situations. Unsupervised learning can combine any number of known heuristics, such as input-output distance (logic depths), gate type, fanout information, and testability measures like Controllability and Observability Program (COP) and Sandia Controllability/Observability Analysis Program (SCOAP) through principal component (PC) analysis, and then the major PC can guide ATPG choices. This study combines three heuristics, distance, COP, and SCOAP. Some heuristic data are complemented and two major PC are obtained. These PC guide backtrace directions in a PODEM ATPG program. For most circuits, the number of backtracks either matches the best of the three heuristics or is lower than all.

Integrated circuit (IC) testing presents complex problems that, when ICs become large, are exceptionally difficult to solve by traditional computing techniques. To deal with unmanageable time complexity, engineers often rely on human “hunches” and “heuristics” learned through experience. Training machines to adopt these human skills is called machine learning (ML). This survey examines applications of ML to testing analog, digital, memory, radio frequency (RF), and other application based ICs. This survey then highlights significant challenges and potential research directions.

This study examines machine intelligence's (MI) ability to enhance automatic test pattern generation (ATPG) by reducing backtracks. In lieu of a conventional heuristic to decide backtracing directions, this study uses an artificial neural network (ANN) trained through PODEM on hard-to-detect faults. Training data contains topological data, testability measures, and backtracking history, and when trained on this data, the ANN guides backtracing in directions unlikely to backtrack. When trained with a single feature (e.g., COP), ATPG performance is comparable to conventional PODEM, and using multiple features further reduces backtracks and ATPG CPU time.

This article presents methods of increasing logic built-in self-test (LBIST) delay fault coverage using artificial neural networks (ANNs) to selecting test point (TP) locations a method to train ANNs using randomly generated circuits. This method increases delay test quality both during and after manufacturing. This article also trains ANNs without relying on valuable third-party intellectual property (IP) circuits. Results show higher-quality TPs are selected in significantly reduced CPU time and third-party IP is not be required for ANN training.