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Jeonghun Gong

dblp:244/9187 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Storage systems · 54% Memory systems · 46%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems
flash and SSD
0.522020
Practical Erase Suspension for Modern Low-latency SSDs · USENIX ATC 2019
A Case for Hardware-Based Demand Paging · ISCA 2020
Storage systems › flash and SSD › SSD performance
low-latency SSD
0.522020
Practical Erase Suspension for Modern Low-latency SSDs · USENIX ATC 2019
A Case for Hardware-Based Demand Paging · ISCA 2020
Operating systems › resource management › memory management › virtual memory
page fault handling
0.412020
A Case for Hardware-Based Demand Paging · ISCA 2020
Operating systems › resource management › memory management
virtual memory
0.412020
A Case for Hardware-Based Demand Paging · ISCA 2020
Memory systems › virtual memory management
demand paging
0.412020
A Case for Hardware-Based Demand Paging · ISCA 2020
Memory systems › memory management
virtual memory
0.412020
A Case for Hardware-Based Demand Paging · ISCA 2020

Methods — techniques the papers use, named apart from their topics

cycle-level simulation · 0.9architectural extension · 0.9
YearPublicationVenuePosition
2020 A Case for Hardware-Based Demand Paging
abstract
The virtual memory system is pervasive in today's computer systems, and demand paging is the key enabling mechanism for it. At a page miss, the CPU raises an exception, and the page fault handler is responsible for fetching the requested page from the disk. The OS typically performs a context switch to run other threads as traditional disk access is slow. However, with the widespread adoption of high-performance storage devices, such as low-latency solid-state drives (SSDs), the traditional OS-based demand paging is no longer effective because a considerable portion of the demand paging latency is now spent inside the OS kernel. Thus, this paper makes a case for hardware-based demand paging that mostly eliminates OS involvement in page miss handling to provide a near-disk-access-time latency for demand paging. To this end, two architectural extensions are proposed: LBA-augmented page table that moves I/O stack operations to the control plane and Storage Management Unit that enables CPU to directly issue I/O commands without OS intervention in most cases. OS support is also proposed to detach tasks for memory resource management from the critical path. The evaluation results using both a cycle-level simulator and a real x86 machine with an ultra-low latency SSD show that the proposed scheme reduces the demand paging latency by 37.0%, and hence improves the performance of FIO read random benchmark by up to 57.1% and a NoSQL server by up to 27.3% with real-world workloads. As a side effect of eliminating OS intervention, the IPC of the user-level code is also increased by up to 7.0%.
Gyusun Lee, Wenjing Jin 0001, Wonsuk Song, Jeonghun Gong, Jonghyun Bae, Tae Jun Ham, Jae W. Lee, Jinkyu Jeong
ISCA4
2019 Practical Erase Suspension for Modern Low-latency SSDs
Shine Kim, Jonghyun Bae, Hakbeom Jang, Wenjing Jin 0001, Jeonghun Gong, SeungYeon Lee, Tae Jun Ham, Jae W. Lee
USENIX ATC5