This paper shows a FeFET-based analog multi-level unit cell for computing-in-memory applications for Deep Neural Networks (DNN). The FeFET-based unit cell performs input-weight multiplication with a Back-End-Of-Line (BEOL) ferro-electric HZO FeFET device on top of standard 180 nm CMOS circuits. The unit cell works with a feedback mechanism which combines an in-house FeFET device to store weights and CMOS transistors underneath to provide outputs in current mode to be integrated over time on a capacitor. Said feedback mechanism compensates for device-to-device variability, and would permit to calibrate a system against time variations, something not usually included in cross-bar solutions. Joint electrical simulations of the FeFET-CMOS circuit are performed with a compact Verilog-A model extracted from the experimental characterization of the FeFET devices. Electrical simulations show that our feedback approach leads to a multi-bit cell with 5-bits of resolution, superior to that of state-of-the-art solutions.

This live demonstration shows a mixed-signal design in 180 nm CMOS technology that runs hyperdimensional computing (HDC) on binary hypervectors with up to 8,192 components. The chip comprises 64 × 128 processing elements (PE) arranged in a 2D mesh with direct connection to their first neighbors. PEs include a 1-bit ALU with a 16 6T-SRAM bank to execute HDC primitives. Hypervector classification is performed through the Hamming distance with current sources in every PE globally connected to an analog computing unit laid down outside the PE array. The overall approach results in tens of nJ of power consumption in inference, which is competitive with state-of-the-art solutions.

This live demonstration shows a mixed-signal Computer In Memory (CIM) macro deep neural network (DNN) integrated circuit in 180 nm CMOS technology for image recognition. Images are coded as pulse width modulation (PWM) signals. DNN weights are stored as voltages in 6T-SRAM memories which drive current sources inside every multiplier. Multipliers are arranged within processing elements laid down in a 2D mesh suitable for image processing. The power consumption per multiplier of the CIM macro is of 0.22 µW, below state-of-the-art competitors following the same multiply and accumulate (MAC) principle.

This paper explores the feasibility of a capacitor-less (CL) low-dropout (LDO) regulator to operate efficiently in a low-voltage environment. The CL-LDO scheme selected is based on a unity-gain feedback configuration around the error amplifier (EA), so that the inclusion of high-value on-chip resistors is avoided and different key parameters, such as the power supply rejection or the noise, are optimized. A comparative analysis has been carried out over the same LDO structure including a bulk-driven and a gate-driven EA, respectively. The pass branch of the voltage regulator is provided with pseudo-class-AB operation, in order to lead to a very small quiescent current in the standby operation mode, whereas a very large current can be delivered to the load when required. Both regulators were designed and fabricated in 180 nm CMOS technology to operate with a maximum supply voltage of 1.8 V. The extensive experimental characterization showed that the bulk-driven LDO can achieve a significantly lower minimum supply voltage, i.e., 0.6 V, as compared to the gate-driven counterpart, 1 V, under the same reference voltage and load current conditions.

A subthreshold input voltage charge pump based on the well-known cross-coupled voltage doubler and using boosted gate voltages for the transfer switches is presented. A level shifter and some inverters, including a novel inverter architecture proposed in this work and referred to as negative low-state voltage inverter, are used to generate the clock signals for the switching transistors with the purpose of significantly improving their drive capability. A complete analysis of the proposed charge pump is provided to highlight the advantages of the implemented structure, revealing the power efficiency improvement when the input voltage is below the threshold voltage of the transistors. An extensive experimental characterization of silicon prototypes in 180 nm CMOS technology was carried out, showing that the proposed scheme is able to pump charge from an input voltage as low as 110 mV. The experimental peak efficiency remains above 70% for input voltages between 180 mV and 400 mV and input power levels from 45 nW to 25$\mu \text{W}$, which are appropriate for different miniaturized transducers implementable on chip.

This paper addresses a mixed-mode CMOS circuit for Hyperdimensional Computing (HDC). HDC is based on the use of binary vectors with thousands dimensions to represent data in a holistic way. During the last years HDC has shown to be a powerful approach to solve classification problems. The proposed circuit architecture in this paper is made up of an array of 128 × 64 (8192) processing units (PUs) with a 1-bit ALU, local memory and connectivity to their 4 nearest neighbors to run the basic operations of HDC, i.e, binding, bundling and permutation. The architecture also includes a module to calculate Hamming distance to address classification. Post-layout simulations of the complete system working on various basic operations in 0.18 μ m CMOS technology are shown.

Neural network mixed-mode hardware accelerators for deep convolutional neural networks (CNN) strive to cope with a high number of input feature maps and increasing bit depths for both weights and inputs. As an example of this need, the ResNet model for image classification comprises 512 3× 3 feature filters in its conv5 layer. This would lead to 4068 multipliers driving a summing node for actual concurrent processing of all the input feature maps, which makes up a challenge in mixed-mode. This paper addresses the design of a 5-bit signed SRAM-based in-memory computing cell in 180 nm 3.3 V CMOS technology, dealing with the impact of increasing the number of input feature maps. The data presented in the paper are based on electrical and post layout simulations.

A capacitor-less (CL) low-dropout (LDO) regulator suitable to be incorporated in an on-chip system with low-voltage micro-energy-harvested supply, is proposed in this contribution. The differential input stage of the error amplifier includes bulk-driven MOS transistors, thus providing the LDO with an output voltage range that extends from the negative rail up to a level very close to the input voltage without the need of using a resistive feedback network. The circuit parameters relying on the feedback factor,$\beta $, are maximized thanks to the use of a unitary value for this parameter. The CL-LDO has been designed and fabricated in standard 180-nm CMOS technology and optimized to operate with an input voltage equal to 0.6 V and a reference level of 0.5 V. The experimental characterization of the fabricated prototypes shows that, under these operating conditions, the LDO is able to deliver a load current above 0.75 mA with a total quiescent current of only 7.0 nA. Furthermore, the proposed voltage regulator is able to operate from input voltages as low as 0.4 V, delivering in this case a maximum load current of 30$\mu \text{A}$.

An ultra-low power LDO regulator with an adaptive biasing error amplifier is presented in this paper. An absolute difference voltage meter circuit section based on super source followers is used to achieve the adaptive biasing scheme. The experimental total quiescent current consumption is as low as 1.88 nA with a measured line sensitivity of 0.13 mV/V in a circuit occupying 1473 μm2of silicon area.