CMOS miniaturization and timing faults due to factors, such as aging, emphasize that embedded processor reliability is a major concern. Among the various aging mechanisms, negative bias temperature instability (NBTI) is encountered as the dominant factor. Techniques against NBTI are mostly based on aggressive Vdd scaling, decelerating aging at the expense of performance degradation. Traditionally, designers use conservative guard-bands to combat timing faults, leading to loss of efficiency. Some other reactive approaches use sensors, requiring hardware modification and large area and debug overheads. According to the literature, two opportunities exist to compensate for the performance loss: instruction timing slacks imposed by static timing analysis (STA) and application computational error resiliency. This article proposes an efficient estimation model for the instruction-level timing slack probability distribution function (PDF) and gives a dynamic approach for statistical timing analysis, which is used for dynamic frequency management to improve performance of both error-resilient and errorsensitive applications. To this aim, we introduce a metric called architecture timing-fault vulnerability factor, considering NBTI and Vdd effects. Simulation results show that the proposed timing slack PDF estimation model has an accuracy of about 94%, which can be used to increase throughput of error-resilient applications up to 3.2 times compared with when the traditional STA is used.

Lifetime reliability management of miniaturized CMOS devices continuously gets more importance with the shrinking of technology size. Neither of existing design-time solutions (like guard-banding) and runtime methods (like reactive monitoring) does efficiently address this issue; rather, proactive approaches, which use runtime aging prediction, are getting more promising to provide resiliency. Among various reliability threatening mechanisms in recent technologies, negative bias temperature instability is the dominant factor; it depends on multiple time-varying operational parameters, including temperature, supply voltage, and stress. This paper proposes an efficient instruction-level stress estimation model; accordingly, it introduces a runtime aging prediction approach for embedded processors, taking simultaneous impacts of the temperature, supply voltage, and stress variations. We propose instruction degradation factor and architecture degradation factor metrics, respectively, for fine-grained stress estimation and recurring runtime aging prediction. We also provide a simulation environment for model validation. Simulation results of several benchmarks show that the proposed stress estimation model has an accuracy of about 92%, indicating that the method is accurate enough, yet simple for runtime usage.