In the Philippines, road pavement damage poses significant threats to road safety, often leading to accidents, vehicular damage, and increased maintenance costs. Typically, actual road surveying is conducted when inspecting road pavement damage, a traditional method that is time-consuming when generating reports about the surveyed road pavement. Requiring labor, expenses, and subjective evaluations, resulting in inaccuracies and inefficiencies in assessing road conditions, which delays maintenance and repair. The main objective of this study is to develop a real-time road damage classification and severity detection using YOLOv8. Using a moving vehicle, a high-resolution camera is mounted, capturing images of road pavement damages in real-time, processed by the NVIDIA Jetson Nano, YOLOv8 as the deep-learning model classifying road pavement damage classes: potholes, cracks, alligator cracks, pumping, and depression, determining it identified severity levels based on the standards and guidelines set by the Department of Public Works and Highways (DPWH). A VK-162 GPS module is incorporated to geotag each detected road damage by recording its latitude and longitude coordinates in real-time for accurate location mapping and detailed reporting of road conditions. The system was evaluated based on its accuracy of detection and the tagged location. The findings of the study suggest that the system is a viable, low-cost, and scalable assessment tool to conduct preliminary assessments of road conditions, providing significant opportunities to reduce manual labor while improving the speed and efficiency of data collection and asset and infrastructure maintenance planning.

This paper presents a novel 6-Gbps variation insensitive input/output (I/O) buffer designed for DDR4 and DDR5 SDRAM data transfer in a 16-nm FinFET CMOS process. Utilizing genetic algorithm (GA) to model process, voltage, and temperature (PVT) variations, the study reveals insights into temperature and voltage effects on FinFET-based, nanoscale buffer characteristics, leading to the removal of the temperature detector circuit to save power and area. Voltage variations, however, significantly impact slew rate, prompting the introduction of a Voltage Detector circuit using ultra-low threshold voltage (ULVT) transistors. Innovative Voltage Level Converter, Pre-Driver, and Digital Logic Control circuits enhance slew rate and throughput while stabilizing the output signal quality. This results in reliable operation at 6.0 Gbps with improved slew rate (17.7%/39.75% for VDDIO =0.8/1.2 V) and duty cycle performance (50.5%/51.4% for VDDIO =0.8/1.2 V) due to PV auto-adjustment; the first in the world. The proposed design effectively addresses the stringent slew rate and data rate requirements of DDR4 and DDR5 SDRAMs, offering advancements in speed, reliability, and efficiency amidst PV variations.

Recent digital pulsewidth modulation (DPWM) researches use multiple clock inputs and long D flip-flop (DFF) arrays, which makes scaling to different DPWM frequencies challenging. This brief demonstrates a DPWM that utilizes a single clock and a Matrix shift array, allowing it to be scaled to any frequency and reducing the effects of clock skew. It has a clock gating technique that selects a specific row of DFFs based on the required % duty cycle. The DPWM design has a dead time generator to prevent shoot-throughs. The DPWM has been fabricated using UMC 180-nm CMOS process. The performance and functionality of the DPWM have been verified through the measured comparisons of % duty ratio, dead time ($T_{dt}$), and output frequency ($f_{\text {out}}$) at input clock frequency ($f_{\text {clk}_{\text {in}}}$) equal to 10$\sim $100 MHz. The DPWM design has a maximum % duty ratio of 90.6%,$T_{dt}$= 1.8 ns, and$f_{\text {out}}$= 6.25 MHz with 3.4-mW power consumption at$f_{\text {clk}_{\text {in}}}$= 100 MHz.

A time-difference amplifier (TDA) with a wide time-difference input range and variable gain is presented in this paper. Its time amplification is performed using novel current source architecture, phase detection, and variable delay circuits. After time amplification, to avoid the current sources for charging and discharging capacitors simultaneously, a reset circuit is added. To widen the input time-difference range, an adjustable current source control is added. The proposed TDA is implemented using TSMC 40-nm CMOS process. The core area is $209.42\times 84.775\mu \mathrm{m}^{2}$. Though our design is driven by a lower supply voltage, it has the widest time-difference input range and the largest FOM among all existing TDAs.

This investigation proposes a computing-in-memory (CIM) design to circumvent the von Neumann bottleneck which causes limited computation throughput for effective artificial intelligence (AI) applications. The proposed CIM performs multiple operations such as single-instruction basic Boolean operations, addition, and signed number multiplication, and multiple functions such as normal mode and retention mode for the built-in self-test (BIST). Its 2T-Switch requires only two transistors to be utilized for static random-access memory (SRAM) array; thus, the arithmetic unit can be chosen easily and the area overhead is minimized. Its ripple carry adder and multiplier (RCAM) unit based on single-ended disturb-free 7T 1-Kb SRAM was developed using the full swing-gate diffusion input (FS-GDI) technology that has full voltage swing resolution, low power consumption, and less chip area cost. Its Auto-Switching Write Back Circuit restores addition and multiplication operations automatically to assigned memory address. The CIM is implemented using the TSMC 40-nm CMOS process, where the core area is$432.81 \times 510.265\,\,\mu \text{m}^{2}$. Among the related works, the proposed CIM performs the most number of operations and functions.

This paper presents the development of an incubation system for autonomous temperature and humidity control using Arduino microcontroller interfaced and coded using LabView programming. The proposed system also includes important functions to hatch eggs which are candling through infertile egg identification using basic image acquisition, and egg turning that employs crank-rocker mechanism and a hatching chamber. It revolves around fusing all the elements of egg incubation and turning it into one device. It functions autonomously without having to consistently check and adjust to obtain optimal parameters. By using its monitoring features, the user can have real-time data of the day-to-day status of the incubator's parameters. The speed of its automatic candling program is 1.129 seconds while the performance of the incubator held an optimal temperature of 36oCelsius with humidity between 40% and 60% with an optimal level of 50%. Lastly, the hatch rate percentage of the incubation using the proposed system is 69.44% while the percentage accuracy result for detecting fertile eggs is 91.43%.