ABSTRACT Current BIM visualization systems tessellate parametric geometry into triangle meshes before rendering, which increases memory usage, introduces faceting on curved surfaces, and adds significant export‐time overhead. We present an end‐to‐end system that preserves parametric shape definitions from BIM models through to GPU ray tracing, bypassing mesh conversion for supported parametric shapes. Our exporter extracts parametric shapes from a BIM authoring tool and encodes them into a compact binary format with two‐tier caching to avoid redundant extraction. Our renderer maps preserved BIM primitives to an instanced GPU scene layout and performs direct ray‐primitive intersections, with mixed‐precision parameter encoding and ray advancement improving memory efficiency and numerical robustness. Evaluation on architectural projects shows that our system achieves a lower GPU memory footprint, produces mathematically exact curved surfaces free of tessellation artifacts, and exports models faster than standard workflows.

As AIs rapidly advance and become more agentic, the risk they pose is governed not only by their capabilities but increasingly by their propensities, including goals and values. Tracking the emergence of goals and values has proven a longstanding problem, and despite much interest over the years it remains unclear whether current AIs have meaningful values. We propose a solution to this problem, leveraging the framework of utility functions to study the internal coherence of AI preferences. Surprisingly, we find that independently-sampled preferences in current LLMs exhibit high degrees of structural coherence, and moreover that this emerges with scale. These findings suggest that value systems emerge in LLMs in a meaningful sense, a finding with broad implications. To study these emergent value systems, we propose utility engineering as a research agenda, comprising both the analysis and control of AI utilities. We uncover problematic and often shocking values in LLM assistants despite existing control measures. These include cases where AIs value themselves over humans and are anti-aligned with specific individuals. To constrain these emergent value systems, we propose methods of utility control. As a case study, we show how aligning utilities with a citizen assembly reduces political biases and generalizes to new scenarios. Whether we like it or not, value systems have already emerged in AIs, and much work remains to fully understand and control these emergent representations.

Complementary field-effect transistors (CFETs) have emerged as promising candidates for next-generation semiconductor devices. CFETs feature a structure with an nMOS (or pMOS) transistor at the bottom and a transistor of the opposite type at the top. CFETs can be classified into Fin-CFETs or GAA-CFETs based on their channel structure. In this study, we compare and analyze these two devices to determine which structure is more favorable for device scaling and which device exhibits better performance per unit area. For a reliable analysis, the threshold voltage was adjusted to be the same for all devices. Initially, to compare the DC performance, the on-state drive currents in both linear mode and saturation mode operations were extracted and compared from the$I_{\mathrm { DS}}$-versus-$V_{\mathrm { GS}}$input-transfer characteristics. Subsequently, complementary metal-oxide-semiconductor inverters were constructed to compare their AC performance. Six parameters were extracted and compared: high-to-low propagation delay ($t_{pLH}$), falling time ($t_{f}$), low-to-high propagation delay ($t_{pLH}$), rising time ($t_{r}$), overshoot voltage ($V_{ov}$), and undershoot voltage ($V_{und}$). Based on the results, we suggest which CFET structure is more suitable for device scaling.

Line edge roughness (LER) is an undesirable phenomenon that arises during semiconductor fabrication processes, causing fluctuations in the characteristics of semiconductor devices and potentially leading to significant yield degradation. Consequently, LER must be meticulously considered before fabricating integrated circuits. In this study, we present an approach for implementing and analyzing LER in vertical channel array transistors (VCATs) with a gate-all-around (GAA) structure for dynamic random access memory applications. Initially, we propose a method for reliably implementing LER in GAA semiconductor devices. Next, we extend the method to more complex structures beyond the basic cylindrical GAA structure. Utilizing the proposed method, we investigate the impact of LER on various VCAT device configurations by examining DC performance metrics such as IOFF, IDS,LIN, IDS,SAT, VT,LIN, VT,SAT, IOV,LIN, and IOV,SAT. Additionally, we explore AC performance metrics (THOLD, TREAD, and TWRITE) through mixed-mode simulations. The results show that the parameters influencing LER-induced fluctuations in VCATs vary depending on the transistor’s operating region (i.e., whether the transistor is turned on or not).

We argue that language-only models don't learn the physical manifestation of language.We present an empirical investigation of visualauditory properties of language through a series of tasks, termed H-TEST.These tasks highlight a fundamental gap between human linguistic understanding and the sensory-deprived linguistic understanding of LLMs.In support of our hypothesis, 1. deliberate reasoning (Chain-of-Thought), 2. few-shot examples, or 3. stronger LLM from the same model family (LLaMA 2 13B → LLaMA 2 70B) has no significant effect on H-TEST performance.We bring in the philosophical case of Mary, who learns about the world in a sensorydeprived environment as a useful conceptual framework to understand how languageonly models learn about the world (Jackson, 1986).Our experiments show that some of the strongest proprietary LLMs stay near random chance baseline accuracy of 50%, highlighting the limitations of linguistic knowledge acquired in the absence of sensory experience.Our code and data are available at .