This article presents an efficient method for modeling and analysis of memristor crossbar array circuit-based neuromorphic computing hardware. A novel volatile memristor-based artificial neuron circuit is proposed, realizing real-time generation of spike sequences, where the amplitude, width, and reserve time of the spikes are all adjustable. Based on proposed neuron circuits and nonvolatile memristor-based artificial synapses, a spike timing-dependent plasticity (STDP) circuit implementation with a simple spike-mapping method is proposed and used for a memristor crossbar array-based spiking neural network (SNN) circuit. A circuit model of a crossbar array combined with a partial equivalent element circuit (PEEC) and volume filament (VFI) is used to calculate the circuit capacitance, inductance, and resistance. It is demonstrated by a transient simulation of a crossbar array circuit that the proposed SNN method can perform image classification tasks, and the recognition accuracy decreases with the frequency increase. From the perspective of affecting the spike sequences and STDP rules, damage caused by device stochasticity, parasitic effects, and skin effect on SNN recognition performance is further analyzed and evaluated.

Spiking Neural Networks (SNNs) have garnered considerable attention as a potential alternative to Artificial Neural Networks (ANNs). Recent studies have highlighted SNNs’ potential on large-scale datasets. For SNN training, two main approaches exist: direct training and ANN-to-SNN (ANN2SNN) conversion. To fully leverage existing ANN models in guiding SNN learning, either direct ANN-to-SNN conversion or ANN-SNN distillation training can be employed. In this paper, we propose an ANN-SNN distillation framework from the ANN-to-SNN perspective, designed with a block-wise replacement strategy for ANN-guided learning. By generating intermediate hybrid models that progressively align SNN feature spaces to those of ANN through rate-based features, our framework naturally incorporates rate-based backpropagation as a training method. Our approach achieves results comparable to or better than state-of-the-art SNN distillation methods, showing both training and learning efficiency.

This paper presents the efficient systematic methods for modeling and analysis of spike signal sequence in crossbar arrays for neuromorphic computing chips. A novel spike signal sequence is proposed, where the ideal spike sequence with only spike time information in the original spiking neural network (SNN) algorithm is mapped onto actual spike waveform by stitching neighboring sequential spikes together with certain overlaps. We thoroughly investigate and analyze the performance of the input encoding as well as the implementation of spike timing dependent plasticity (STDP)-based SNN on memristor crossbar arrays with the proposed spike signal sequence. A detailed circuit model of a crossbar array, consisting of resistance, capacitance and inductance derived by the partial equivalent element circuit (PEEC) method, is created to simulate the training process of SNN. The proposed spike signal sequence is demonstrated that is able to achieve accurate input encoding as well as high recognition accuracy when it is used to perform the classification task on MNIST handwritten digits. The spike signal sequence is further analyzed and assessed in terms of the main factors affecting its encoding accuracy and the parasitic effects of crossbar arrays on its robustness.

This article presents a novel circuit modeling method for online training and testing process of the neuromorphic chip crossbar array based on the resistive random access memory (RRAM). A modified RRAM compact model is developed to realize the fast and accurate update of multiple conductance levels. Two training mechanisms with and without write-verify scheme are modeled and investigated for classifying MNIST handwritten digits and both achieve a good recognition accuracy of more than 96%. The parasitic model of the unit cell of interconnects is constructed by the domain decomposition method (DDM) and the partial equivalent element circuit (PEEC) method, which is suitable to build up a crossbar array of any size. The impact of parasitic effects of interconnects on the recognition accuracy with and without write-verify scheme is analyzed and compared. The weights trained with write-verify scheme show better robustness to parasitic noises but training with write-verify scheme spends a longer time processing the same amount of data.