Lamellar directed self-assembly (DSA) technology in combination with the self-aligned via (SAV) process has emerged as a novel and promising choice for via/contact layer fabrication, where a via between Metal-$x$and Metal-$(x+1)$is generated at the intersection of a wire segment on Metal-$(x+1)$and a rectangular and perpendicular guiding template. Compared to the highly investigated cylindrical DSA, lamellar DSA does not suffer from the overlay error of generated holes and thus can have better yield, and it also benefits from the better flexibility of various via pitches a single template can produce. A state-of-the-art work has addressed the guiding template design problem for the new process, and an integer linear programming (ILP) formulation that can optimally solve the problem as well as a simple heuristic approach are proposed. However, solving the ILP formulation is time consuming, and the heuristic method suffers from unignorable degradation in solution quality due to several algorithm deficiencies. In this article, we propose an enhanced and efficient template design algorithm flow for the lamellar DSA and SAV process by using graph monomorphism for pattern conflict check in multiple patterning lithography. Experimental results show that the proposed flow can greatly reduce the numbers of conflicts and short templates and is almost as efficient as the existing heuristic approach.

Directed self-assembly (DSA) with block copolymers (BCP) has become a promising lithography technology for generating tiny features in integrated circuits. There have been many existing studies investigating the design methodologies using cylinder-forming BCP for via/contact layer manufacturing. However, cylindrical DSA suffers from the limited natural pitch of generated holes and the displacement errors due to guiding template distortions. Consequently, only few feasible hole patterns are manufacturable with a template and the unsatisfactory yield is still one of the major concerns. On the other hand, lamellar DSA using lamella-forming BCP emerges as another solution for hole generation, which in combination with the self-aligned via (SAV) process is immune to hole displacement errors and able to produce various linear hole patterns. In this paper, we propose the first work of guiding template design for lamellar DSA by using the SAV process and multiple patterning lithography (MPL). An integer linear programming (ILP)-based approach and a heuristic method are respectively proposed that consider the design constraints induced by lamellar DSA with SAV. Experimental results demonstrate the optimality of the ILP-based approach, and the heuristic method can also efficiently derive near-optimal solutions.

In order to support the pad-limited application-specific integrated circuit (ASIC) designs, the flip chip package is used and provides the highest chip density compared to other packaging technologies. In this paper, we propose the first work of peripheral-input and -output (I/O) free-assignment flip-chip routing considering practical bump pad and I/O pad constraints and flexibilities. Unlike previous studies regarding all nets as the same, we differentiate signal and power/ground nets and set different bump pad assignment constraints for substrate layout optimization. In our flow, a global routing-based I/O-bump assignment algorithm is proposed with a multicommodity flow network model. Afterward, two detailed routing algorithms minimizing the total wirelength are presented. Finally, a dynamic programming (DP)-based I/O pad planning technique is applied to further reduce the number of wire bends. Experimental results based on modified industrial cases show that our algorithm flow not only achieves 100% routability of all testcases but also minimizes total wirelength, total wire bends, and bump utilization.