Congestive heart failure (CHF) is an acute syndrome that results from ventricular dysfunction and progresses in four stages. Its timely detection can reverse heart damage and save lives. This work proposes a low-power, computationally efficient VLSI architecture to detect CHF using a single-lead ECG signal for the first time. This architecture employs a novel wavelet function-based electrocardiogram (ECG) feature extraction method and a random forest (RF) classifier, which can classify regular beats from CHF beats using a subject-oriented approach. Using ECG signals from publicly available datasets, BIDMC-CHF and MIT-BIH NSRDB, the proposed architecture achieves 90.5% accuracy, having a power consumption of$0.1~\mu W$when implemented using TSMC 40-nm bulk CMOS technology as an ASIC. The low power consumption of the proposed architecture enables it to be utilized efficiently for real-time ECG analysis in wearable devices.

Ventricular arrhythmia (VA) is the most critical cardiac anomaly among all arrhythmia beats. Thus, it becomes imperative to predict the occurrence of VA to avoid sudden casualties caused by these arrhythmia beats. In the past, only a few hardware designs have been proposed to predict VA using various features derived from electrocardiogram (ECG) signals and processed using machine learning classifiers. However, these designs are either complex or need more prediction accuracy. Therefore, a deep neural network (DNN)-based co-processor for arrhythmia prediction is proposed in this article. It can predict VA at least$15 \ \min $before its occurrence with 91.6% accuracy. Co-processor architecture for arrhythmia prediction (CoAP) uses an optimal feature vector extracted from the ECG signal and an optimized DNN, using a novel approximate multiplier (AM). CoAP operates at 12.5 kHz and consumes$4.69~\mu \text { W}$when implemented using SCL$180\text {-nm}$bulk CMOS technology. The low power realization of the proposed design and its higher accuracy, compared with well-known state-of-the-art methods, make it suitable for wearable devices.

Continuous monitoring of the electrical activity of heart signals using wearable Internet of Healthcare Things (IoHTs) devices plays a crucial role in decreasing mortality rates. However, this continuous monitoring using an electrocardiogram (ECG) or vectorcardiogram (VCG) generates huge clinical data. Moreover, these devices are constrained in terms of ON-chip storage, data transmission capacity, and power. Thus, handling a large amount of data is difficult with these devices, making it necessary to compress these data for storage and transmission. Lossless or near-lossless data compression solves this problem, ensuring that no relevant physiological/clinical information is lost in the compression process. Therefore, low-power, resource-efficient, and lossless VLSI architectures are proposed in this article to compress multichannel ECG/VCG data. The designs are tested using the PTB database for both ECG and VCG data and can achieve compression ratios (CRs) of 3.857 and 4.45 with minimal power and area requirements making them suitable for low-power wearable healthcare devices.

Atrial fibrillation (AF) is a recurrent and life-threatening disease leading to rapid growth in the mortality rate due to cardiac abnormalities. It is challenging to manually diagnose AF using electrocardiogram (ECG) signals due to complex and varied changes in its characteristics. In this article, for the first time, an end-to-end edge-enabled machine learning-based VLSI architecture is proposed to classify ECG excerpts having AF from normal beats. Researchers have found that abnormal atrial activity is confined to the low-frequency range through the decades. Therefore, in the proposed work, this frequency band is directly analyzed for AF detection, which has not previously been discussed. The proposed architecture is implemented using 180-nm bulk CMOS technology consuming$11.098~\mu {\mathrm{ W}}$at$25~ {\text {kHz}}$and exhibits an accuracy of 92.37% for class-oriented classification and 81.60% for subject-oriented classification. The low-power realization of the proposed design, as compared to the state-of-the-art methods, makes it suitable to be used for wearable devices.

The Cooperative Co-evolution framework is an effective approach for decomposing large scale global optimization problems into multiple sub-components. Every subcomponent uses different optimization algorithms which evolve cooperatively and are independent of each other. These subcomponents contribute in a different way to the overall improvement of the optimal solution. Hence, the computation cost can be decreased by separating out the stagnant subcomponents of the population. Therefore, it is appropriate to allocate resources in an intelligent manner to increase the computational efficiency. In this paper, we illustrate a decomposition strategy to solve large scale global optimization problems which is scalable to millions of variables. The proposed strategy improves computational efficiency and enables embracing parallelization. The framework presented in this paper constitutes Cooperative Co-evolution based Genetic Algorithm with Scalar Distance Grouping technique (CCGA-SDG) derived from Cooperative Co-evolution based Genetic Algorithm (CCGA). In our proposed scheme, a novel scalar distance grouping technique is employed that collates the dependent variables together. The stagnant sub-components of the population are detected using this grouping method and resource reallocation is performed accordingly to increase the computational efficiency. Using our proposed methodology, a benchmark function $f_{6}$ of CEC'08 benchmark composed of 10 million variables is evaluated in 1759.79 seconds using 04 processors connected with Message Passing Interface (MPI) exhibiting better accuracy as compared to other methods. Moreover, for ${f}3$ and $f_{6}$ functions we achieve a better accuracy and for rest of the benchmark functions we achieve acceptable solutions.