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Ravi Goel

dblp:246/3102 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
0000-0003-1921-8221ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 56% Electronic design automation · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › semiconductor device modeling
compact modeling
0.712023
Robust Compact Model of High-Voltage MOSFET's Drift Region · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Electronic design automation › technology computer-aided design
device simulation
0.712023
Robust Compact Model of High-Voltage MOSFET's Drift Region · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Integrated circuit design
analog and mixed-signal circuits
0.212023
Robust Compact Model of High-Voltage MOSFET's Drift Region · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023

Methods — techniques the papers use, named apart from their topics

voltage-dependent formulation · 0.7SPICE simulation · 0.7
YearPublicationVenuePosition
2023 Robust Compact Model of High-Voltage MOSFET's Drift Region
abstract
This brief presents a compact model to capture the major difference between high-voltage (HV) and low-voltage MOSFETs, i.e., the carrier velocity saturation effect in the drift region of HV MOSFETs. We discuss the numerical and behavioral issues that can arise in SPICE simulations with the existing current-dependent formulation in Berkeley-Short-Channel-IGFET model (BSIM) for HV transistors. We then demonstrate how a voltage-dependent formulation can mitigate them without losing simplicity and accuracy. We also validate the proposed model against experimental data of HV transistors.
Girish Pahwa, Ravi Goel, Garima Gill, Harshit Agarwal, Yogesh Singh Chauhan, Chenming Hu
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3