Control and Status Registers (CSRs) are fundamental to the RISC-V architecture, providing a versatile interface for managing processor state, system configuration, and functionality like exception handling, debugging, and performance monitoring. However, their implementation in FPGA-based systems poses challenges due to the inherent constraints of FPGA resources. The need for atomic parallel access to all CSRs, coupled with limitations of conventional LUT-based multiplexing, increases logic depth and resource usage , degrading Fmax in large-scale implementations. This work explores these obstacles and introduces optimized mechanisms to improve CSR handling efficiency. A minimal microarchitectural environment was built to isolate and evaluate multiple access strategies, retaining only components essential to CSR interaction. Leveraging a heterogeneous design tailored to FPGA capabilities—featuring BRAM for decoding, DSPs for multiplexing, and LUTs, CARRYs and flip-flops to facilitate routing—the proposed CSR subsystem achieves performance enhancements ranging from 50% to over 300%, contingent upon configuration. The top-performing implementation reaches 250 MHz on Artix-7 FPGAs while simultaneously reducing area and dynamic power. These results challenge prevailing reliance on abstract electronic design, highlighting that hardware-aware low-level methodologies can yield superior quality-of-results (QoR) over pure behavioral descriptions. More broadly, the findings inform datapath optimization involving decoding and multiplexing in performance-critical and resource-constrained digital architectures.

In recent decades, mixed-criticality systems have been widely adopted to reduce the complexity and development times of real-time critical applications. In these systems, applications run on a separation kernel hypervisor, a software element that controls the execution of the different operating systems, providing a virtualized environment and ensuring the necessary spatial and temporal isolation. The guest code can run unmodified and unaware of the hypervisor or be explicitly modified to have a tight coupling with the hypervisor. The former is known as full virtualization, while the latter is known as para-virtualization. Full virtualization offers better compatibility and flexibility than para-virtualization at the cost of a performance penalty. LEON is a processor family that implements the SPARC V8 architecture and whose use is widespread in the field of space systems. To the best of our knowledge, all separation kernel hypervisors designed to support the development of mixed-criticality systems for LEON employ para-virtualization, which hinders the adaptation of real-time operating systems. This article presents the design of a Virtualization Monitor that allows guest real-time operating systems to run virtualized on LEON-based systems without needing to modify their source code. It is designed as a stand-alone component within a hypervisor and incorporates a set of techniques such as static binary rewriting, automatic code generation, and the use of operating system profiles. To validate the proposed solution, tests and benchmarks have been implemented for three guest systems, RTEMS, FreeRTOS, and Zephyr, analyzing the overhead introduced in certain situations characteristic of real-time applications. Finally, the same benchmarks have been run on AIR, one of the hypervisors that uses para-virtualization. The results obtained show that the use of the proposed techniques allows us to obtain similar results to those obtained using para-virtualization without the need to modify the source code of the guest real-time operating systems.

Abstract The development process of on-board software applications can benefit from model-driven engineering techniques. Model validation and model transformations can be applied to drive the activities of specification, requirements definition, and system-level validation and verification according to the space software engineering standards ECSS-E-ST-40 and ECSS-Q-ST-80. This paper presents a model-driven approach to completing these activities by avoiding inconsistencies between the documents that support them and providing the ability to automatically generate the system-level validation tests that are run on the Ground Support Equipment and the matrices required to complete the software verification. A demonstrator of the approach has been built using as a proof of concept a subset of the functionality of the software of the control unit of the Energetic Particle Detector instrument on-board Solar Orbiter.

The objective of this investigation is to implement a technology that provides measurements of quality of service (QoS) of established local area networks. Improvements of the required infrastructure for applications of telelearning (videoconference, electronic blackboard, shared applications…) are implemented with a minimal cost. We are implementing features of ATM on Ethernet local area networks, through the protocol "Cells In Frame" (CIF). This protocol encapsulates ATM cells in Ethernet frames using CIF specification. Values of measured parameters reveal that the implementation provides the ATM quality of service necessary for telelearning traffic type.