In this paper, we propose a novel approach for the real-time estimation of chip-level spatial power maps for commercial Google Coral M.2 TPU chips based on a machine-learning technique for the first time. The new method can enable the development of more robust runtime power and thermal control schemes to take advantage of spatial power information such as hot spots that are otherwise not available. Different from the existing commercial multi-core processors in which real-time performance-related utilization information is available, the TPU from Google does not have such information. To mitigate this problem, we propose to use features that are related to the workloads of running different deep neural networks (DNN) such as the hyperparameters of DNN and TPU resource information generated by the TPU compiler. The new approach involves the offline acquisition of accurate spatial and temporal temperature maps captured from an external infrared thermal imaging camera under nominal working conditions of a chip. To build the dynamic power density map model, we apply generative adversarial networks (GAN) based on the workload-related features. Our study shows that the estimated total powers match the manufacturer's total power measurements extremely well. Experimental results further show that the predictions of power maps are quite accurate, with the RMSE of only 4.98mW/mm2, or 2.6% of the full-scale error. The speed of deploying the proposed approach on an Intel Core i7-10710U is as fast as 6.9ms, which is suitable for real-time estimation.

In this work, we propose a fast full-chip thermal numerical analysis approach based on an enhanced physics-informed neural networks (PINN) framework. The new method, called ThermPINN, leverages both PINN-based DNN optimization framework and analytic solutions of simplified thermal problems for solving thermal partial differential equations (PDE). The resulting ThermPINN leads to more efficient training speed of DNN networks and more scalability for solving large PDE problems. Specifically, we propose to partially enforce physics laws based on closely related analytic solutions to simpler problems. As a result, we are able to significantly reduce the number of variables in the loss function and easily meet boundary conditions. To consider the impact of various ambient temperatures and effective convection coefficients, which are influenced by different design parameters and run-time conditions, we develop a parameterized thermal analysis technique. This technique enables design space exploration and uncertainty quantification (UQ), which are critical for ensuring the reliability of integrated circuits under various operating conditions. The numerical results on alpha21264 processor show that the proposed ThermPINN has 2× speedup and 3× better accuracy over the state-of-the-art thermal simulator, VarSim. The experimental results for 2-D full-chip thermal analysis of 3171 cases show that the proposed parameterized ThermPINN considering both training and inference time can achieve a 6× speedup over commercial COMSOL with an average mean absolute error (AE) of 0.47 K. In terms of training time, the proposed parameterized ThermPINN is 11× faster than the parameterized plain PINN with similar accuracy. The UQ analysis with 5000 samples for maximum temperature propagated from ambient temperature shows that the parameterized ThermPINN and parameterized plain PINN are 113× and 22× faster than COMSOL, respectively.

In this paper, we propose a novel machine learning-based approach, called PostPInn- Em, for solving the partial differential equations for stress evolution in a confined metal interconnect multi-segment trees during the post-voiding stage for fast electromigration (EM) check for interconnects. The new approach is based on an enhanced two-stage Physics-Informed Neural Networks (PINN) framework in which the physics law for a single wire is enforced first and then atomic flux conservation and stress continuity at the inter-segment junctions of wire segments are then fulfilled to reduce the number of variables of loss functions for the fast training process. Existing two-stage PINN method uses supervised learning method for modeling a single wire under various atomic flux conditions for the first stage, which turns out to be much more difficult for post-voiding phase due to arbitrary non-zero initial conditions. To mitigate this problem, we propose a new closed-form parameterized formula for stress solution of single wires with variable bound-ary conditions based on the Laplace transformation methods. Furthermore, we derive the analytic solutions for wire segment with and without voiding as not all the wire segments will have voids during the post-voiding phase. Numerical results on some synthesized multi-segment interconnects show that the proposed PostPINN-EM can achieve more than 100X speedup compared to FEM based tool COMSOL with the expense of less than 1% accuracy. Compared to the state of the art tool EMspice v1.0 [1], this method can achieve more than 25X speedup with similar accuracy compared to golden results from COMSOL.

In this work, we propose a novel physics-informed sparse regression (PISR) framework to solve stress evolution (described by Korhonen’s equations) in general multisegment wires using an unsupervised learning scheme. Unlike the existing physics-informed neural network (PINN) framework, the PISR method trains the trainable weights through the Moore–Penrose generalized inverse algorithm used in extreme learning machine (ELM), which is extremely faster than the backpropagation algorithm. To improve the accuracy of PISR for complex multisegment interconnects, we employ domain decomposition schemes in both space and time. For each subdomain, we use different trainable weights but the same shared neural network to represent each subsolution, which leads to more efficient memory usage. Furthermore, we propose to use sparse matrix techniques to accelerate the training speed of the PISR method and prove that the resulting PISR has linear time complexity for analyzing tree-structured interconnects. Finally, we divide the time into many time intervals and apply an autoregressive model to simulate each time interval in sequence to further improve scalability and reduce memory cost so that the PISR method can perform EM analysis for large-scale multisegment interconnects. Experimental results on different kinds of interconnect structures show that the proposed PISR method has the same accuracy level as the numerical methods. The results on$N_{T}$T-junctions interconnect trees show that the proposed PISR method indeed demonstrates true linear time complexity. Furthermore, PISR can deliver$8.9\times $,$20.6\times $, and$1284\times $speedups over the recently proposed semi-analytic method (ASOV), finite difference method accelerated with model order reduction (FDM-MOR), FDM for the interconnect with$N_{T}= 5000$, respectively. Furthermore, we show that PISR also achieves an$818\times $speedup in training over the plain PINN method based on the traditional backpropagation algorithm.

Thermoelectric cooler (TEC) is a promising active cooling device to remove the localized hot spots precisely in VLSI chips. In this article, we use a novel implicit physics-constrained neural networks (called IPCNNs) to build a surrogate model for the single TEC device with the reduction from 3-D to 1-D. First, the surrogate model represented by the deep neural networks (DNNs) allows parameterization of key design and running parameters, such as current density, length, and thermal boundary conditions of the TEC. Second, the proposed method tries to partition the physics laws into two different groups, which then are enforced by supervised learning and physics-informed neural networks (PINNs) framework sequentially. Such implicit PCNN scheme can lead to much faster training speed and better convergent accuracy for the unsupervised training. The existing plain PINN enforces all the physics laws via the loss functions and the network tends to have very slow training speed and a large convergent error for large problems. An extreme learning machine (ELM) is used for the networks in the first stage. Compared with fully connected network (FCN) trained by the traditional back-propagation algorithm, ELM can be easily trained and converges much faster. Furthermore, by leveraging the differential nature of the DNN model, we can directly estimate the derivative of the cooling heat flux with respect to current density instead of using a finite difference approximation. The calculated derivatives are used to find the optimal current density to achieve maximum cooling heat flux via Newton’s method. Last but not least, we propose a novel hybrid finite element neural network (FENN) method to perform thermal analysis of the VLSI chip system with the TEC device. The DNN model is embedded into COMSOL through the heat flux boundary conditions. Experimental results show that the machine learning-based method can achieve about$8.5\times $speedup with good accuracy than the COMSOL-based finite element method. Furthermore, the proposed IPCNN is more stable and accurate than the existing PINN. The proposed FENN can have a$5.1\times $speedup and$5.4\times $memory reduction over the traditional numerical method.

This article presents a fast full-chip electromigration (EM) aware IR drop constrained optimization framework, namedGridNetOpt, for on-chip power grid networks accelerated by deep neural networks (DNNs). Compared to the existing linear programming-based methods, the new method employs more flexible conjugate gradient-based optimization to size the wire width of the power grids. To mitigate the high cost of sensitivity calculation of the adjoint network using full-chip IR drop analysis at every iteration step, the sensitivity is computed via a trained conditional generative adversarial network (CGAN). The new method exploits the differentiable characteristics of DNNs for fast sensitivity computation. The sensitivity, which is the node voltage with respect to wire resistance, will guide the search direction during the optimization process. In order to consider more accurate EM failure effects, the training data is obtained from the power grids under different wire widths and current loads analyzed by a state-of-the-art full-chip multiphysics-based coupled EM-IR drop analysis tool. This is in contrast with the existing linear programming-based methods, in which only immortal wires or wires with nonzero resistance can be dealt with. Numerical results on a number of synthesized power grid benchmarks from ARM Cortex-M0 processor designs show that the proposedGridNetOptcan lead to at least an order of magnitude speedup over the conjugate gradient-based method using the traditional adjoint network method. Compared to the previous localized power grid fixing work withGridNet,GridNetOptleads to smaller area overhead for all the benchmarks we tested. It can also reduce IR drops for power grid circuits with immortal wires, which is not possible with the localizedGridNetmethod.

2.5D chiplet-based technology promises an efficient integration technique for advanced designs with more functionality and higher performance. Temperature and related thermal optimization, heat removal are of critical importance for temperature-aware physical synthesis for chiplets. This paper presents a novel graph convolutional networks (GCN) architecture to estimate the thermal map of the 2.5D chiplet-based systems with the thermal resistance networks built by the compact thermal model (CTM). First, we take the total power of all chiplets as an input feature, which is a global feature. This additional global information can overcome the limitation that the GCN can only extract local information via neighborhood aggregation. Second, inspired by convolutional neural networks (CNN), we add skip connection into the GCN to pass the global feature directly across the hidden layers with the concatenation operation. Third, to consider the edge embedding feature, we propose an edge-based attention mechanism based on the graph attention networks (GAT). Last, with the multiple aggregators and scalers of principle neighborhood aggregation (PNA) networks, we can further improve the modeling capacity of the novel GCN. The experimental results show that the proposed GCN model can achieve an average RMSE of 0.31 K and deliver a 2.6× speedup over the fast steady-state solver of open-source HotSpot based on SuperLU. More importantly, the GCN model demonstrates more useful generalization or transferable capability. Our results show that the trained GCN can be directly applied to predict thermal maps of six unseen datasets with acceptable mean RMSEs of less than 0.67 K without retraining via inductive learning.

Electromigration (EM) becomes a major concern for VLSI circuits as the technology advances in the nanometer regime. The crux of problem is to solve the partial differential Korhonen equations, which remains challenging due to the increasing integrated density. Recently, scientific machine learning has been explored to solve partial differential equations (PDE) due to breakthrough success in deep neural networks and existing approach such as physics-informed neural networks (PINN) shows promising results for some small PDE problems. However, for large engineering problems like EM analysis for large interconnect trees, it was shown that the plain PINN does not work well due the to large number of variables. In this work, we propose a novel hierarchical PINN approach, HierPINN-EM for fast EM induced stress analysis for multi-segment interconnects. Instead of solving the interconnect tree as a whole, we first solve EM problem for one wire segment under different boundary and geometrical parameters using supervised learning. Then we apply unsupervised PINN concept to solve the whole interconnects by enforcing the physics laws in the boundaries for all wire segments. In this way, HierPINN-EM can significantly reduce the number of variables at plain PINN solver. Numerical results on a number of synthetic interconnect trees show that HierPINN-EM can lead to orders of magnitude speedup in training and more than 79× better accuracy over the plain PINN method. Furthermore, HierPINN-EM yields 19% better accuracy with 99% reduction in training cost over recently proposed Graph Neural Network-based EM solver, EMGraph.

Electromigration (EM) becomes a major concern for VLSI circuits as the technology advances in the nanometer regime. With Korhonen equations, EM assessment for VLSI circuits remains challenged due to the increasing integrated density. VLSI multisegment interconnect trees can be naturally viewed as graphs. Based on this observation, we propose a new graph convolution network (GCN) model, which is called EMGraph considering both node and edge embedding features, to estimate the transient EM stress of interconnect trees. Compared with recently proposed generative adversarial network (GAN) based stress image-generation method, EMGraph model can learn more transferable knowledge to predict stress distributions on new graphs without retraining via inductive learning. Trained on the large dataset, the model shows less than 1.5% averaged error compared to the ground truth results and is orders of magnitude faster than both COMSOL and state-of-the-art method. It also achieves smaller model size, $4\times$ accuracy and $14\times$ speedup over the GAN-based method.

Computing the electric potential and electric field is important for modeling and analysis of VLSI chip and high speed circuits. For instance, it is an important step for DC analysis for high speed circuits as well as dielectric reliability and capacitance extraction for VLSI interconnects. In this paper, we propose a new data-driven meshless 2D analysis method, called PCEsolve, of electric potential and electric fields based on the physics-constrained deep learning scheme. We show how to formulate the differential loss functions to consider the Laplace differential equations with voltage boundary conditions for typical electrostatic analysis problem so that the supervised learning process can be carried out. We apply the resulting PCEsolve solver to calculate electric potential and electric field for VLSI interconnects with complicated boundaries. We show the potential and limitations of physics-constrained deep learning for practical electrostatics analysis. Our study for purely label-free training (in which no information from FEM solver is provided) shows that PCEsolve can get accurate results around the boundaries, but the accuracy degenerates in regions far away from the boundaries. To mitigate this problem, we explore to add some simulation data or labels at collocation points derived from FEM analysis and resulting PCEsolve can be much more accurate across all the solution domain. Numerical results demonstrate that the PCEsolve achieves an average error rate of 3.6% on 64 cases with random boundary conditions and it is 27.5× faster than COMSOL on test cases. The speedup can be further boosted to ~ 38000× in single-point estimations. We also study the impacts of weights on different components of loss functions to improve the model accuracy for both voltage and electric field.

With technology scaling approaching atomic levels, IC test and diagnosis of complex System-on-Chips (SoCs) become overwhelming challenging. In addition, sustaining the reliability of transistors as well as circuits at such extreme feature sizes, for the entire projected lifetime, also become profoundly difficult. This holds even more when it comes to emerging technologies that go beyond convectional CMOS in which the underlying physics are not yet fully understood. In this special session paper, we describe the usage of machine learning in several test and reliability related areas. First, we demonstrate the vital role that machine learning can play in IC test showing the importance of explainability as a frontier for machine learning in IC test. Afterwards, we discuss how novel physics-informed neural networks can be employed to model electrostatic problems in VLSI designs. This is essential to mitigate the deleterious effects of of time dependent dielectric breakdown, which is the key source of reliability degradations. Finally, we discuss the major sources of reliability degradations at the transistor level in advanced technology nodes such as transistor aging phenomena and self-heating effects as well as we demonstrate how machine learning approaches can further help in developing reliable emerging technologies.

In this work, we propose an accurate full chip steady-state power density map estimation method for the commercial multi-core microprocessors. The new approach is based on the measured steady-state thermal maps (images) from an advanced infrared (IR) thermal imaging system to ensure its accuracy. The new method consists of a few steps. First, based on the first principle of heat transfer, 2D spatial Laplace operation is performed on the given thermal map to obtain the so-called raw power density map, which consists of both positive and negative values due to the steady-state nature and boundary conditions of the microprocessors. Then based on the total power of the microprocessor from an online CPU monitoring tool, we develop a novel scheme to generate the actual real positive- only power density map from the raw power density map. At the same time, we develop a novel approach to estimating the effective thermal conductivity of the microprocessors. To further validate the power density map and the estimated actual thermal conductivity of the microprocessors, we construct a thermal model with COMSOL, which mimics the real experimental set up of measurement used in the IR imaging system. Then we compute the thermal maps from the estimated power density maps to ensure the computed thermal maps match the measured thermal maps using FEM method. Experimental results on intel i7-8650U 4-core processor show 1.8°C root-mean-square- error (RMSE) and 96% similarity (2D correlation) between the computed thermal maps and the measured thermal maps.

In this paper, we propose a novel transient full-chip thermal map estimation method for multi-core commercial CPU based on the data-driven generative adversarial learning method. We treat the thermal modeling problem as an image-generation problem using the generative neural networks. In stead of using traditional functional unit powers as input, the new models are directly based on the measurable real-time high level chip utilizations and thermal sensor information of commercial chips without any assumption of additional physical sensors requirement. The resulting thermal map estimation method, called ThermGAN can provide tool-accurate full-chip transient thermal maps from the given performance monitor traces of commercial off-the-shelf multi-core processors. In our work, both generator and discriminator are composed of simple convolutional layers with Wasserstein distance as loss function. ThermGAN can provide the transient and real-time thermal map without using any historical data for training and inferences, which is contrast with a recent RNN-based thermal map estimation method in which historical data is needed. Experimental results show the trained model is very accurate in thermal estimation with an average RMSE of 0.47°C, namely, 0.63% of the full-scale error. Our data further show that the speed of the model is faster than 7.5ms per inference, which is two orders of magnitude faster than the traditional finite element based thermal analysis. Furthermore, the new method is ~4x more accurate than recently proposed LSTM-based thermal map estimation method and has faster inference speed. It also achieves ~2x accuracy with much less computational cost than a state-of-the-art pre-silicon based estimation method.

Electromigration (EM) is a major failure effect for on-chip power grid networks of deep submicron VLSI circuits. EM degradation of metal grid lines can lead to excessive voltage drops (IR drops) before the target lifetime. In this paper, we propose a fast data-driven EM-induced IR drop analysis framework for power grid networks, named GridNet, based on the conditional generative adversarial networks (CGAN). It aims to accelerate the incremental full-chip EM-induced IR drop analysis, as well as IR drop violation fixing during the power grid design and optimization. More importantly, GridNet can naturally leverage the differentiable feature of deep neural networks (DNN) to obtain the sensitivity information of node voltage with respect to the wire resistance (or width) with marginal cost. Grid-Net treats continuous time and the given electrical features as input conditions, and the EM-induced time-varying voltage of power grid networks as the conditional outputs, which are represented as data series images. We show that GridNet is able to learn the temporal dynamics of the aging process in continuous time domain. Besides, we can take advantage of the sensitivity information provided by GridNet to perform efficient localized IR drop violation fixing in the late stage design and optimization. Numerical results on 36000 synthesized power grid network samples demonstrate that the new method can lead to 105× speedup over the recently proposed full-chip coupled EM and IR drop analysis tool. We further show that localized IR drop violation fix for the same set of power grid networks can be performed remarkably efficiently using the cheap sensitivity computation from GridNet.

Electromigration (EM) analysis for complicated interconnects requires the solving of partial differential equations, which is expensive. In this paper, we propose a fast transient hydrostatic stress analysis for EM failure assessment for multisegment interconnects using generative adversarial networks (GANs). Our work is inspired by the image synthesis and feature of generative deep neural networks. The stress evaluation of multi-segment interconnects, modeled by partial differential equations, can be viewed as time-varying 2D-images-to-image problem where the input is the multi-segment interconnects topology with current densities and the output is the EM stress distribution in those wire segments at the given aging time. We show that the conditional GAN can be exploited to attend the temporal dynamics for modeling the time-varying dynamic systems like stress evolution over time. The resulting algorithm, called EM-GAN, can quickly give accurate stress distribution of a general multi-segment wire tree for a given aging time, which is important for full-chip fast EM failure assessment. Our experimental results show that the EM-GAN shows 6.6% averaged error compared to COMSOL simulation results with orders of magnitude speedup. It also delivers 8.3× speedup over state-of-the-art analytic based EM analysis solver.