Guillermo Díez-Señorans

dblp:246/5996 · DBLP profile ↗
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4ranked-venue papers
0as first author
4since 2021 · last 2026
0000-0001-9131-0861ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021Security and privacy · 1 · 1 since 2021
YearPublicationVenuePosition
2026 PUF optimization for IoT device authentication
abstract
Two critical aspects in IoT are security and resource consumption. Physically Unclonable Functions (PUFs) are hardware security primitives that exploit the inherent manufacturing variations of integrated circuits to generate unique identifiers. Due to their uniqueness and resistance to cloning, they are widely used for IoT device authentication. In this work, a novel approach to enhance the identifiability of compensated measurement PUFs is introduced. This method involves applying specific weight masks to the parameters extracted from the PUF entropy source before conducting comparisons to determine the output bit. This technique has been tested on several types of PUFs constructed using public datasets. As a result, it has been observed that the Equal Error Rate ( EER ) can be greatly improved, up to two orders of magnitude. The main advantage of this technique is that it does not modify the architecture of the compensated measurement PUF (which is interesting for IoT devices, as it does not require extra resources), while it also has proven to be generalizable, i.e., the optimal mask parameters can be found using a small set of devices and, then, generalized to a different bigger set of devices. This way, this proposal contributes to the development of novel authentication schemes for IoT devices, addressing both security and resource efficiency, critical issues in IoT environments. • A novel optimization technique to improve the identifiability of a compensated measurement PUF and its theoretical justification. • The optimization requires only a small subset of devices as a training dataset, enabling generalization to a larger population of devices. • The implementation of this technique and test using different types of PUFs constructed using public databases. • The implementation of one technique which does not require additional hardware resources based on initializing counters to a certain value.
Raúl Aparicio-Téllez, Miguel Garcia-Bosque, Guillermo Díez-Señorans, Concepción Aldea, Santiago Celma
Comput. Secur.3
2024 Enhancing Identifiability of PUFs with Built-in Compensation through Nonlinear Transformations
abstract
In this work, we propose a novel strategy to increase the identifiability of any PUF that uses the compensated measuring technique. The proposed strategy consists of applying certain Nonlinear Transformations before performing the comparisons of the parameters extracted from the entropy source to obtain the output bit. With this purpose, we apply this technique to different types of PUFs constructed using public datasets, as well as a PUF implemented by ourselves. The results obtained show a significant improvement in the Inter-HD of the PUF of up to 6 percentage points. Likewise, we also show that for some cases, it is possible to improve identifiability by up to two orders of magnitude.
Raúl Aparicio-Téllez, Miguel Garcia-Bosque, Guillermo Díez-Señorans, Santiago Celma
ISCAS3
2024 Novel PUF based on Generalized Galois Ring Oscillators with 10-15 EER and 0.53% BER
abstract
In this work, a novel Weak Physically Unclonable Function (PUF) suitable for FPGA based on 11-LUT Generalized Galois Ring Oscillators (GenGAROs) has been proposed. The GenGARO-PUF has been implemented in 40 Artix-7 FPGAs and 128-bit sequences have been generated for each device. The proposed PUF presents an average Inter-HD of 49.89 %, an average Intra-HD of 1.68 % and an Equal Error Rate (EER) of 2.71 · 10-15. Our proposal has been compared to other state-of-the-art PUFs as well as with a conventional Ring Oscillator PUF (RO-PUF) implemented in the exact same locations of the FPGA. This analysis shows that the proposed PUF can outperform previously proposed PUFs in terms of EER. Finally, an alternative architecture of the proposal using 3-LUT GenGAROs has been implemented and analyzed, proving that it is possible to maintain a high identifiability (EER=6.43 · 10-14) using considerably fewer resources of the FPGA.
Raúl Aparicio-Téllez, Miguel Garcia-Bosque, Guillermo Díez-Señorans, Santiago Celma
ISCAS3
2022 Design and characterisation of a Physically Unclonable Function on FPGA using second-order compensated measurement
abstract
Physically unclonable functions (PUFs) have become an important area of study in the field of hardware security. In this paper we have designed a ring oscillator PUF (RO-PUF) implemented it in FPGA and characterised it using a new concept: second-order compensated measurement by two-bit extraction. The results show that it is possible to use two quality bits to generate the response, thus improving the performance compared to conventional RO-PUFs.
Jorge Fernández-Aragón, Guillermo Díez-Señorans, Miguel Garcia-Bosque, Santiago Celma
VLSI-SoC2