Network embedding is a technique that maps nodes of the network to low-dimensional vector spaces. Role, as an essential notion in social networks, holds significant importance in comprehending relationships between nodes and their attributes. Thus, role-based network embedding has emerged as the latest tool for analyzing networks and achieving network embedding applications. To address the problems of existing network embedding methods, such as 1) inefficient network wandering, 2) only neighborhood information is considered while ignoring role, and 3) multiple roles were not being addressed, this paper proposes the method called Network Splitting Multi-Role Network Embedding by Quantum walk (MRSQ). It firstly splits the multi-role nodes, and then obtains role structure by quantum walk utilizing its superposition ability. Next, the model fuses the neighborhood information of the nodes using a weighted characteristic function to obtain the feature of roles. Finally, the model designs variational auto-encoder to reduce the noise, which improves the quality of the role network embedding. The node classification experiments on real network datasets show that the F1 and AUC scores of MRSQ outperform the baseline method by up to 18.3%, thus reflecting the superiority and robustness of the model.

This paper presents an energy-efficient calibration-free hybrid noise-shaping SAR ADC for low-power high-resolution applications. A high-efficiency 2nd-order fully- passive noise-shaping technique is adopted in this circuit to achieve higher in-band noise attenuation for a better signal-to-noise ratio (SNR). Mismatch error shaping with digital prediction is used to mitigate harmonic distortions without affecting ADC's dynamic range, therefore greatly improving the signal-to-noise-and-distortion ratio (SNDR) and spurious- free dynamic range (SFDR). The prototype ADC is designed in 55 nm CMOS and occupies an area of 0.126 mm2. It consumes 7.426 μW at 400 kS/s sampling rate from a 1 V supply. The post-layout simulated SNDR is 91.05 dB for a 6.25 kHz bandwidth without any calibration, resulting in a Schreier figure of merit (FoMS) of 180.30 dB and a Walden figure of merit (FoMW) of 20.40 fJ/conversion-step.

This paper presents a floating-ring hybrid amplifier (FRHA) insensitive to PVT and common-mode variation, in which a floating power supply is used for the third stage. In differential-mode, the transistors of third stage are forced into the subthreshold region, which improves the loop gain and quickly realizes the pole separation, reducing the times of the oscillation convergence. As for common-mode, a pair of small cross-coupled NMOS is added as the load of first stage, which sharply reduced the common-mode gain without affecting the differential-mode gain much. Moreover, the floating power supply provided by the capacitor has natural common-mode stability. To achieve PVT robustness, a PVT tracking circuit for charging the power supply capacitor is designed, which solves the early shutdown of the third stage caused by insufficient capacitor charge at fast process corner and reduces oscillation cycles due to insufficient phase margin at slow process corner. This FRHA has been applied to a 12-bit 200MS/s pipelined-SAR ADC as residue amplifier (RA) in 65nm CMOS process. The simulation result achieves 67.95dB SNDR at Nyquist frequency and 1.2Vpeak-peak input, yielding a Walden FoM of 5.57 fJ/con-step.

This paper presents a 96.5% peak efficiency adaptive ON-time controlled buck converter with 0.001-500 mA load range for internet of things. A novel positive feedback controlled comparator is presented, with its bias current dynamically increased to accelerate the transient responses while maintaining low power consumption. Besides, the power gating scheme and a sub-nA voltage reference is implemented to achieve ultra-low overall quiescent current, leading to an outstanding conversion efficiency. Designed and simulated in a 0.18μm CMOS process, the prototype shows an undershoot voltage of 43 mV and recovery time of 2.8 µs during a load transient from 10 μA to 500 mA, with a total quiescent current of 60 nA. The proposed design shows efficiencies of 95.4%, 96.5% and 91.2% when the load current is 10 μA, 100 μA, and 500 mA, respectively.