Modern Field-Programmable Gate Arrays (FPGAs) are widely utilized across various fields, including artificial intelligence accelerators and Internet of Things (IoT) devices, due to their flexibility and low-cost development potential. However, the problem of “recycled FPGAs” being fraudulently sold as new has grown increasingly severe. This raises significant concerns about reliability degradation caused by performance deterioration, especially in critical applications such as medical and communication systems. Many studies have proposed methods for detecting recycled FPGAs based on delay degradation analysis using Ring Oscillators (ROs). However, the state-of-the-art approach requires a comprehensive evaluation of paths within all lookup tables, leading to increased testing costs and database management overhead. To address this issue, a method combining exhaustive fingerprinting (X-FP) methodology with an advanced RO design is proposed, where a statistical Virtual Probe (VP) model is used to predict the delay of the RO. This research aims to achieve high-accuracy predictions with fewer data points by employing Gaussian Process Regression (GPR) instead of the VP model. This demonstrates that, with actual silicon data, the proposed custom (GPR) improves prediction accuracy by 20% compared with state-of-the-art VP model methods with 50% less training data. The two proposed models demonstrated better performance than Naive GPR, achieving 9% and 7% higher prediction accuracy, respectively. The predictions were further verified using an optimized Autoencoder. The model successfully detected both 10-days and 14-days aged FPGAs among the new ones, achieving 100% overall accuracy using only 10% and 3% training data, respectively. While although the training data predicted by the VP can also detect aged FPGAs, it cannot properly classify all aged and non-aged FPGAs in both 3% and 10% training scenarios. Finally, for further verification in the case of both new and aged FPGA, after prediction, the logistic regression classifier was trained with both old and new FPGA data, achieving 100% correct classification.

Hardware Trojan detection through side-channel analysis in physical chips is very challenging due to the presence of manufacturing process variations. Numerous Trojan detection approaches are in the literature. However, most of them are limited to netlist level identification and unable to explain the process variation issue in post-silicon chips. In this work, we propose a new detection technique with delay side-channel analysis that can detect all types of Trojans under the presence of high process variations. The technique is termed as zero delay deviation (ZDD) that is capable of diminishing the effect of all variations and other noise sources to identify the Trojan presence in chips. The ZDD approach is achieved by 1) a novel equal-delay circuit partitioning, 2) placing a highly secured camouflaged ring oscillator PUF per partition to generate equal-delay challenge-response pairs that delivers the knowledge of variation trends, 3) generating Identical Delay (ID) neighboring pairs for both, partitions and PUF designs that ensure nullifying the variation effects upon comparing them. The ZDD is examined through an intra-referencing of ID pairs with PUF-RD pairs in ISCAS’85 and 89 benchmarks. 10,000 virtual chips are generated by Monte Carlo simulation considering all physical characteristics of a real chip. Results demonstrate that the proposed approach can successfully detect Trojans even if it consists of a single gate. A comparison to the state-of-the-art shows the method superiority over others.

With the expansion of the semiconductor supply chain, recycled field-programmable gate arrays (FPGAs) have become a serious concern. Several methods for detecting recycled FPGAs by analyzing the ring oscillator (RO) frequencies have been proposed; however, most assume the presence of known fresh FPGAs (KFFs) as the training data used for machine-learning-based classification, which is an impractical assumption. In this study, we propose a novel KFF-free recycled FPGA detection method based on an unsupervised anomaly detection scheme. As the RO frequencies in the neighboring logic blocks on an FPGA are similar because of systematic process variation, our method compares the RO frequencies and does not require KFFs. The proposed method efficiently identifies recycled FPGAs through outlier detection using direct density ratio estimation. Experiments using Xilinx Artix-7 FPGAs demonstrate that the proposed method successfully distinguishes two recycled FPGAs from 10 fresh FPGAs. In contrast, a conventional KFF-free recycled FPGA detection method results in certain misclassification.

This research work presents a novel method for the detection of recycled field-programmable gate arrays (FPGAs). In this method, delay information of all paths in look-up tables (LUTs) of configurable logic blocks in the FPGAs is analyzed exhaustively by employing an advanced ring oscillator (RO) design. Although the proposed X-FP characterization technique can accurately capture the aging degradation of each path of all LUTs in the FPGA, it considerably increases the RO measurement cost. Furthermore, X-FP yields a large amount of measurement data causing the "curse of dimensionality" problem when used as a feature vector in the machine learning (ML) based detection system. To combat these challenges while applying the X-FP characterization, we additionally propose two techniques for realizing accurate and efficient recycled FPGA detection: compressed sensing (CS) based prediction and with-in die (WID) modeling based feature engineering. In CS-based estimation, we incorporate the virtual probe (VP) technique for low-cost RO measurement. The WID modeling properly reflects the process variation of each FPGA, and model parameters extracted by the modeling are utilized as a feature vector in the ML-based detection to classify target FPGAs as either fresh or aged. Through experiments using commercial FPGAs, we demonstrate that the proposed method combining the VP and WID modeling on the X-FP characterization achieves high-accuracy recycled FPGA detection at a low measurement cost.

In this study, a novel method for the detection of recycled field-programmable gate arrays (FPGAs) is proposed. This method is based on with-in die (WID) process variation model over an exhaustive path characterization [referred to as exhaustive-fingerprint (X-FP)]. In the proposed method, X-FP is capable of fully characterizing frequencies on all paths in look-up tables (LUTs) using advanced ring oscillator (RO) design to exhaustively capture deterioration by aging. Although machine learning (ML)-based classification is often used for recycled FPGA detection, X-FP yields a large amount of measurement data, which cannot be appropriately handled by typical ML algorithms, if they are used as a feature vector. The proposed method utilizes the model parameters extracted by WID variation modeling as the feature vector in the ML algorithm. These model parameters simply and accurately represent the process variation for each FPGA. In this way, the ML-based fresh/recycled classification works very well with the simple feature vector. Experiments using 50 commercially available FPGAs reveal that X-FP can capture the degradation effects, which cannot be detected by conventional methods. Moreover, the WID modeling achieves 99.6% feature size reduction per one FPGA. It also demonstrates that the model parameters exhibit good distance properties between fresh and aged FPGAs. Additionally, the ML-based classification which uses a one-class support vector machine can successfully detect 2 aged FPGAs (48 h accelerated aging) without any misclassification and another 4 aged FPGAs (24 h accelerated aging) with a very few misclassifications as fresh FPGAs.

We propose a novel recycled field programmable gate array (FPGA) detection method based on with-in die (WID) variation modeling. Model parameters extracted by the WID modeling simply but accurately represent the process variation of each FPGA, and thus, by using the model parameters as feature vector, machine learning effectively classifies target FPGAs into fresh or aged. Through experiment on commercial circuit simulator, the proposed method achieves 99.6% feature vector size reduction per FPGA with showing 96.0% detection accuracy; while our silicon result using commercial FPGA demonstrates the model parameters have a good distance properties between fresh and aged.

Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled fieldprogrammable gate arrays (FPGAs). On the other hand, it requires a large number of measurements of ROs for all FPGAs before shipping, and thus leads to measurement cost inflation. In this research, we propose a low-cost recycled FPGA detection method using a virtual probe (VP) technique based on compressed sensing. The VP technique enables us to accurately predict the spatial process variation on a die from a very small number of sample measurements. Using the estimated process variation as a supervisor, machine-learning algorithm classifies target FPGAs into recycled or fresh. Through experiments using circuit simulation, our method achieves more than 96% detection accuracy using one-class support vector machine where only 20% samples of the frequency are used at the best case. Silicon measurement results on Xilinx Artix-7 FPGAs also demonstrate the efficiencies of the proposed method.