Edge AI has become the cornerstone of many applications. Yet, progress is limited by the large complexity of training a deep neural network (a DNN). hyperdimensional computing (HDC) is positioned as an alternative approach for Edge AI that is compact enough to enable training. The main challenge for an HDC model is to maintain its key features while balancing high inference accuracy with efficiency. A simple binary HDC model lacks accuracy, while the computational complexity of a floating-point model is too high. This work presents FixedHD, a novel 16-bit fixed-point HDC model enabling training at the Edge. FixedHD achieves an accuracy similar to floating-point model while lowering computational complexity. The model is supported by a customized RISC-V processor tailored to speedup both training and inference. The processor is extended with advanced HDC-specific instructions, a vector unit to utilize HDC’s parallel nature, and, for the first time, approximate computing to exploit its robustness. Further, memory requirements are reduced by quantizing mathematical functions and reducing the large HDC encoding matrix by up to 390 x. Compared to the baseline processor, inference and training are accelerated on average by 6.9 x and 3 x, respectively. The energy consumption is reduced by 4.6 x and 1.9 x at the cost of an increase in area by 45 %. The inference accuracy remains at the high level of floating-point models despite the heavy quantization and approximation.

A sixth order complex filter based on the usage of a newly proposed fully differential current conveyor (FDCC) is presented in this paper. The FDCC new structure is based on usage of differential difference operational floating amplifier (DDOFA) and floating current source circuits. The block is realized using 0.25 mum CMOS technology under plusmn1.5 V power supply. PSPICE simulation for the FDCC is done for testing the block. The simulation shows that the FDCC has plusmn0.5 V input dynamic range, 95 MHz 3-dB frequency at output terminal under 10 KOmega load and 7.21 mW total power dissipation. The FDCC is used to realize first order complex filter with 1 MHz center frequency and second order complex filter at 500 KHz center frequency. Finally; using cascading technique, a sixth order complex filter at 500 KHz center frequency is proposed. The proposed filter is suitable for applications like Bluetooth receivers. All the proposed filter circuits are simulated using ADS simulator.