Time-dependent dielectric breakdown (TDDB) is a critical contributor to wear-out failures in semiconductors, aggravated by scaling of thin-oxide fabrication processes. Stress-induced leakage current (SILC) that increases with wear-out in these thin-oxide transistors correlates to TDDB hard failure risk, however existing in-field monitoring solutions struggle to characterize picoamp currents and maintain effective bias during measurements. We present a sensor for in-field predictive TDDB failure risk assessment of gate dielectrics based on SILC characterization via a current integration measurement scheme. The sensor enables constant voltage bias and current amplification during measurement within a simple 5-transistor topology. Our design is fabricated in a 12nm FinFET process and subjected to accelerated aging stress using an in-house test platform to verify the design, with eight sensor variants showing good correlation with simulation results. Observed SILC degradation and soft breakdown events allow for detailed analysis and comparison of transistor wear-out across gate oxide stack-ups, enabling future semiconductor in-field failure risk management strategies.

Ring oscillators are widely used for monitoring wear-out in semiconductor devices, providing a holistic view of degradation resulting from multiple mechanisms simultaneously affecting the inverter stages. In this work we present a ring oscillator sensor architecture for isolated monitoring of the contributions of bias temperature instability (BTI) and hot carrier injection (HCI) stress regimes in both NMOS and PMOS transistors. The design contributes a topology for HCI stress isolation, explicit consideration for degradation of auxiliary transistors, and enhanced comparative analysis capability through an interwoven oscillator layout technique. The sensor variants are implemented in a 12nm FinFET process then stressed and measured using a custom automated wear-out test system built using Rust. Our measurement results agree with simulations and illustrate the differences in degradation between stress regimes in non-planar transistors.

Wear-out reliability in integrated circuits is becoming an increasingly complex topic, with emerging high-reliability markets demanding stricter requirements, diverse workloads making stress characterization challenging, and sub-5nm device scaling aggravating variability in degradation processes. Efforts to tackle these complexities can benefit greatly from sophisticated techniques that effectively capture the variable and uncertain nature of semiconductor wear-out mechanisms. True-to-life stochastic modelling and computational Bayesian inference offer promising avenues in this pursuit but are difficult to leverage without a framework for specifying and evaluating wear-out models that capture this probabilistic information. We present a temporal wear-out simulator, Gerabaldi, as a foundation for enabling these statistical techniques for integrated circuit reliability engineering. The simulator introduces novel capabilities including layered stochastic parameter modelling, fully agnostic design enabling custom degradation model and stress test specifications, and wear-out model definition forms compatible with modern computational Bayesian inference frameworks. Here, we frame Gerabaldi within the context of existing wear-out analysis methods. We then present its key design features and two detailed example applications to illustrate the simulator’s capabilities.

We introduce a methodology to predict degradation in an SoC device undergoing a thermally accelerated aging process. SoCs are usually stressed at high temperatures and voltages (above nominal) to accelerate their aging so that their reliability under nominal conditions can be predicted. Here we focus on the thermal acceleration process. We implement a ring oscillator-based test structure and consider its free-running frequency as our reference parameter to measure degradation. We analyze 500 hours of BTI-induced degradation behavior at different temperatures and observed that the final degradation can be confidently predicted from the measurements in first half of the experiment. This observation provides a new research avenue to predict reliability test results, such as HTOL, which lasts for 1000 hours and has a negative impact on the product’s time to market.

Laser scalpels are utilized across a variety of surgical and dermatological procedures due to their precision and non-contact nature. This paper presents a novel laser scalpel system for superficial laser therapy applications. The system integrates a RGB-D camera, a 3D triangulation sensor and a carbon dioxide (CO2) laser scalpel for computer-assisted laser surgery. To accurately ablate targets chosen from the color image, a 3D extrinsic calibration method between the RGB-D camera frame and the laser coordinate system is implemented. The accuracy of the calibration method is tested on phantoms with planar and cylindrical surfaces. Positive error and negative error, as defined as undershooting and overshooting over the target area, are reported for each test. For 60 total test cases, the root-mean-square of the positive and negative error in both planar and cylindrical phantoms is less than 1.0 mm, with a maximum absolute error less than 2.0 mm. This work demonstrates the feasibility of automated laser therapy with surgeon oversight via our sensor system.