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Uday Ananth

dblp:246/8872 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
High-performance computing · 44% Electronic design automation · 44% Performance modeling and evaluation · 13%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing › parallel i/o
i/o variability
0.412019
MOANA: Modeling and Analyzing I/O Variability in Parallel System Experimental Design · IEEE Trans. Parallel Distributed Syst. 2019
Electronic design automation › design for manufacturability › statistical design › statistical circuit design
performance variation modeling
0.412019
MOANA: Modeling and Analyzing I/O Variability in Parallel System Experimental Design · IEEE Trans. Parallel Distributed Syst. 2019

Methods — techniques the papers use, named apart from their topics

nonlinear regression · 0.4linear regression · 0.4
YearPublicationVenuePosition
2019 MOANA: Modeling and Analyzing I/O Variability in Parallel System Experimental Design
abstract
Exponential increases in complexity and scale make variability a growing threat to sustaining HPC performance at exascale. Performance variability in HPC I/O is common, acute, and formidable. We take the first step towards comprehensively studying linear and nonlinear approaches to modeling HPC I/O system variability in an effort to demonstrate that variability is often a predictable artifact of system design. Using over 8 months of data collection on 6 identical systems, we propose and validate a modeling and analysis approach (MOANA) that predicts HPC I/O variability for thousands of software and hardware configurations on highly parallel shared-memory systems. Our findings indicate nonlinear approaches to I/O variability prediction are an order of magnitude more accurate than linear regression techniques. We demonstrate the use of MOANA to accurately predict the confidence intervals of unmeasured I/O system configurations for a given number of repeat runs - enabling users to quantitatively balance experiment duration with statistical confidence.
Kirk W. Cameron, Ali Anwar 0001, Yue Cheng 0001, Bo Li 0032, Uday Ananth, Jon Bernard, Chandler Jearls, Thomas Lux, Yili Hong 0001, Layne T. Watson, Ali Raza Butt
IEEE Trans. Parallel Distributed Syst.6