Approximate Computing (AC) is an emerging design paradigm that exploits the error-resiliency of specific applications to trade-off between accuracy, performance, area, and power. Nonetheless, fault tolerance remains an open issue in AC since hardware (HW) faults that are caused, for example, by radiation-induced effects, environmental disturbances, or aging/wear-out phenomena, can lead to an arithmetic error out of application specification boundaries. In this work, we guard approximate adders against HW faults by selectively inserting Hardware Fault Detection (HFD) redundancy, i.e., parity code/parity prediction or Double Modular Redundancy (DMR) into the Approximate Arithmetic Circuits (AACs). Specifically, we insert HFD only to the 1-bit adder cells of AACs that can cause an arithmetic error out of their specifications when corrupted by HW faults. Therefore, our proposed approach introduces less area and delay overheads than blindly duplicating the whole AAC. We employ our methodology to state-of-the-art approximate adder models (either low-latency approximate adder or approximate full adder models) to prove that our proposed technique inserts HFD into the AACs without negating their original approximation gains.

Approximate Computing Techniques (ACTs) take advantage of resilience computing applications to trade off among output precision, area, power, and performance. ACTs can lead to significant gains at affordable costs when efficiently implemented on Field Programmable Gate Array– (FPGA) based accelerators. Although several novel ACTs works have been proposed for FPGA accelerators, their applicability to high-assurance systems has not been explored as much. ACTs are becoming necessary in many critical Edge computing systems, such as self-driving cars and Earth observation satellites, to increase computational efficiency. However, an important question comes to mind when targeting critical systems: Does ACT optimization negatively affect the reliability of the system and how can one find optimal design architectures that blend classic mitigation techniques like Triple Modular Redundancy with approximation- and precise-based arithmetic hardware units to achieve the best possible computational efficiency without compromising dependability? This work aims to solve this research problem by introducing a Design Space Exploration (DSE) methodology that employs ACTs in arithmetic units of the design and identifies Pareto-optimal microarchitectures that balance all relevant gains of ACTs, such as area, speed, power, failure rate, and precision, by inserting the correct amount of approximation in the design. In a nutshell, our DSE methodology has formulated the DSE with a Multi-Objective Optimization Problem (MOP). Each Pareto-optimal solution of our tool finds which arithmetic units of the design to implement with precise and approximate circuits and which units to selectively triplicate to remove single points of failure that compromise system reliability below acceptable thresholds. We also suggest another formulation of the DSE into a Single-Objective constraint Optimization Problem (ScOP) producing a single optimal point, and that the user may demand, as a less time-consuming alternative to the MOP if a complete Pareto-front is not needed. Our methodology generates fault-tolerant versions of the Pareto-optimal approximate designs (or simple optimized approximate designs if the ScOP choice is picked) by selectively applying mitigation techniques in a way that the overheads of redundant resources for fault-tolerance do not negate the gains of approximation in comparison to the fault-tolerant versions of the precise design. We evaluate our method on two FPGA-based accelerators: a JPEG encoder and an H.264/Advanced Video Coding decoder. Our experimental results show significant gains in area, frequency, and power consumption without compromising output quality and system reliability compared to classic solutions that replicate all or a part of the resources of the precise design to increase dependability metrics.

In this paper, we evaluate the impact of approximate adders on the reliability of FPGA-based accelerators for applications that present inherent error resilience. We perform an exhaustive fault injection campaign to examine the effects of single bit upsets (SEUs) in the adders in the DCT block of a JPEG encoder IP core. We analyse how much the reliability of the JPEG encoder deteriorates with the use of approximate instead of accurate adders.