The heightened sensitivity of circuit behavior to manufacturing processes is surging in sub-nanometer nodes, presenting a formidable challenge for high-dimensional performance modeling. Estimating circuit performance variations resulting from process randomness in upcoming technology nodes aids in implementing appropriate countermeasures to handle them. Addressing this, we introduce a multi-node transfer learning method for predicting the performance of VLSI digital circuits. The proposed method facilitates Zero-shot Learning in future technology nodes based on insights gained from analyzing the circuit’s process-induced behavior in established nodes. The approach is fast, scalable, and robust, leveraging digital standard cell characterization that can be applied to estimate the performance of a wide array of intricate circuits. Experimental results affirm the approach’s exceptional data efficiency, achieving a speed increase of up to 104times, all the while maintaining superior accuracy compared to traditional simulators.

Analog circuit characterization is a pivotal phase in the design process, serving to validate their performance. It ensures that design choices lead to optimization, ultimately resulting in reliable and robust designs. The conventional, resource-intensive circuit characterization using traditional simulation tools is being supplanted by Machine Learning surrogate models, providing computational advantages. Nevertheless, these models tend to be specific to particular circuits, demanding significant design efforts and often lacking reusability for other designs and topologies. In this paper, we introduce a Unified Neural Network Architecture that is versatile and computationally efficient. It offers a streamlined and effective approach for modeling a diverse array of analog circuits prone to process, voltage, and temperature variations. Experimental trials conducted on various circuits in CMOS 180nm, 65nm and 28nm technologies demonstrate a mean average percentage error of less than 1%, affirming the effectiveness and reusability of the proposed architecture. This leads to substantial savings in design time, computational resources, and characterization costs.

Aggressive scaling down of transistor dimensions has made process-aware circuit modeling a crucial task. Achieving accurate circuit modeling requires lengthy and resource-intensive simulations. Machine Learning-based surrogate models, offering computational efficiency and speed, are viable alternatives to traditional simulators. This paper introduces a meta-learning approach designed to accurately capture process-induced variations in the leakage power of VLSI circuits. The impact of a wide range of fluctuations in operating conditions, including temperature (-55°C to 125°C) and supply voltage (±10%) has also been incorporated for leakage modeling. The proposed meta-learning model is versatile, enhancing the performance of underlying baseline machine-learning models while eliminating the need for time-consuming hyperparameter optimization. Our experiments on leakage estimation using 16 and 7 nanometer FinFET technology nodes demonstrate an average improvement of up to 50% and 48% in Mean Absolute Percentage Error compared to stand-alone baseline models.

Designing robust performance models for modern complex digital circuits in the face of rapidly accelerating process variations is a critical yet demanding task. This paper introduces an efficient statistical performance modeling approach for VLSI digital circuits that incurs minimal computational expense. The fundamental concept involves capitalizing on knowledge gained from circuit modeling in one technology node to streamline the modeling process in another. This is achieved by merging previously established statistical models of process technology with a limited set of simulation data from a subsequent process technology through transfer learning. Comprehensive experiments conducted across diverse technology nodes demonstrate that the proposed framework is robust, precise, efficient in data usage, and computationally superior to other cutting-edge performance modeling techniques.

Approximate Computing has paved way for elaborate savings in design area and latency of modern system architectures processing images or signals, by a deliberate yet tolerable loss of functional accuracy. This paper thus proposes a design of an approximate multiplier based on the efficient Toom-Cook algorithm, that has a lower complexity of O(Nlogd(zd-1)) than O(N2), for order d. Inherent integer divisions in the algorithm has restricted its feasibility in hardware, unless without suitable approximation. On an average, the proposed multiplier achieves 53%, 18% and 57% improvements in area, delay and power only with less than 1% mean error. Owing to these benefits due to lower computational complexity, the multiplier can be configured to achieve significant savings with a high quality output and that suits well to the nature of the speech processing systems, hence the design works well for the epoch extraction system in speech.

In this paper, we propose an accurate and computationally efficient Gradient Boosting approach for the estimation of statistical variations aware leakage power and propagation delay in the CMOS/FinFET standard digital cells. The proposed model estimates the leakage power and propagation delay w.r.t variations in process, temperature (-55°C to 125°C) and supply voltage(±10% variations). The distinguishing feature of the proposed approach is its compatibility with both CMOS and FinFET technologies. Moreover, the performance of the proposed model is consistent with various technology nodes. Exhaustive tests report an average error of <; 1% in 16nm CMOS and FinFET standard digital cells w.r.t analog HSPICE simulations with several orders increase in computational speed. Further, the complex cell estimation can be carried out through precharacterized standard cells abstaining longer simulations.